Usage Aware NUMA Process Scheduling

• US 20120317371A1
• Filed: 06/19/2012
• Published: 12/13/2012
• Est. Priority Date: 06/19/2012
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Concurix Corporation
• Inventors: Gounares, Alexander G.
• Granted Patent: US 9,047,196 B2
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0817 using directory methods

Abstract

Processes may be assigned to specific processors when memory objects consumed by the processes are located in memory banks closely associated with the processors. When assigning processes to threads operating in a multiple processor NUMA architecture system, an analysis of the memory objects accessed by a process may identify processor or group of processors that may minimize the memory access time of the process. The selection may take into account the connections between memory banks and processors to identify the shortest communication path between the memory objects and the process. The processes may be pre-identified as functional processes that make little or no changes to memory objects other than information passed to or from the processes.

Claims

1. A method comprising:

operating a computer system comprising a plurality of processor groups and a plurality of memory banks, each of said processor groups having a corresponding one of said memory banks;

while operating said computer system, receiving a first process comprising instructions that operate on a first memory object;

identifying a first memory bank containing said first memory object;

selecting a first processor being contained in a first processor group, said first processor group corresponding to said first memory bank; and

executing said first process on said first processor.

2. The method of claim 1, said first memory object being one of a plurality of memory objects operated on by said first process.

3. The method of claim 2, said first memory object being a largest memory object of said plurality of memory objects.

4. The method of claim 2 further comprising:

organizing said plurality of memory objects corresponding to said memory banks, each of said memory objects being stored in one of said memory banks; and

selecting said first memory bank as comprising a largest amount of memory consumed by said first process.

5. The method of claim 4, said memory objects being consumed by said first process.

6. The method of claim 2 further comprising:

organizing said plurality of memory objects corresponding to said memory banks, each of said memory objects being stored in one of said memory banks; and

selecting said first memory bank as comprising a largest number of memory objects operated upon by said first process.

7. The method of claim 1, said first process being identified as a functional process.

8. The method of claim 7, said functional process changing no state other than input or output memory objects explicitly defined for said functional process.

9. The method of claim 7, said functional process being defined in a functional language.

10. The method of claim 9, said functional language being one of a group composed of:

Erlang;

Scala;

F#;

Lisp;

Clojure;

OCaml; and

Haskell.

11. The method of claim 7, said first process being identified as a functional process by static analysis of said first process.

12. The method of claim 11, said static analysis identifying a set of input data, a set of output data, and a set of side effects data, said set of side effects data being smaller than said set of input data.

13. The method of claim 12, said set of side effects data being smaller than a sum of said set of input data and said set of output data.

14. A system comprising:

a plurality of processors, each of said processors belonging to one of a plurality of processor groups;

a plurality of memory banks, each of said memory banks being assigned to one of said processor groups;

a process scheduler that;

receives a first process comprising instructions that operate on a first memory object;

identifies a first memory bank containing said first memory object;

selects a first processor being contained in a first processor group, said first processor group corresponding to said first memory bank; and

executes said first process on said first processor.

15. The system of claim 14 further comprising:

an analysis engine that;

receives executable code;

identifies a functional block within said executable code, said functional block having defined input and output memory objects and changes no other memory objects during execution; and

transmits said functional block as said first process to said process scheduler.

16. The system of claim 15, said process scheduler that further:

identifies said first process as being a functional process.

17. The system of claim 16, said first process being identified as said functional process by a compiler.

18. The system of claim 17, said compiler being a just in time compiler.

19. The system of claim 14 further comprising:

an operating system;

an execution environment within said operating system, said execution environment comprising memory management functions for executing code, said process scheduler operating within said execution environment.

20. The system of claim 14, said process scheduler being an operating system level function.