Method for Reducing Stress in Epitaxial Growth

• US 20120319160A1
• Filed: 11/09/2011
• Published: 12/20/2012
• Est. Priority Date: 11/09/2011
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Toshiba Techno Center Inc. (Toshiba Corporation)
• Inventors: Lester, Steven D.
• Granted Patent: US 8,552,465 B2
• Time in Patent Office: Days
• US Class Current: 257/103
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

A device and method for making the same are disclosed. The device includes a substrate having a first TEC, a stress relief layer overlying the substrate, and crystalline cap layer. The crystalline cap layer overlies the stress relief layer. The cap layer has a second TEC different from the first TEC. The stress relief layer includes an amorphous material that relieves stress between the crystalline substrate and the cap layer arising from differences in the first and second TECs at a growth temperature at which layers are grown epitaxially on the cap layer. The device can be used to construct various semiconductor devices including GaN LEDs that are fabricated on silicon or SiC wafers. The stress relief layer is generated by converting a layer of precursor material on the substrate after the cap layer has been grown to a stress-relief layer.

Claims

1. A device comprising:

a substrate having a first TEC;

a stress relief layer overlying said substrate; and

a crystalline cap layer overlying said stress relief layer, said cap layer having a second TEC different from said first TEC,

wherein said stress relief layer comprises an amorphous material that relieves stress between said crystalline substrate and said cap layer arising from differences in said first and second TECs at a growth temperature at which layers are grown epitaxially on said cap layer.

2. The device of claim 1 wherein said stress layer comprises an alloy of In and Ga that is liquid at said growth temperature.

3. The device of claim 1 wherein said substrate comprises a silicon wafer.

4. The device of claim 1 wherein said substrate comprises a SiC wafer.

5. The device of claim 1 wherein said cap layer comprises a material from the GaN family of materials.

6. The device of claim 1 further comprising:

a first layer comprising a material of a first conductivity type overlying said stress relief layer;

an active layer overlying said first layer, said active layer generating light when holes and electrons recombine therein; and

a second layer comprising a material of a second conductivity type.

7. The device of claim 6 further comprising a first contact connected to said first layer and a second contact connected to said second layer, said active layer generating light when a potential is provided between said first and second contacts.

8. The device of claim 6 wherein said cap layer is part of said first layer.

9. The device of claim 6 wherein said first layer is deposited on said cap layer.

10. A method for fabricating a semiconductor device, said method comprising:

depositing a precursor stress relief layer on a substrate characterized by a first TEC;

epitaxially depositing a first semiconductor layer on said precursor stress relief layer, said layer being characterized by a second TEC, different from said first TEC; and

converting said precursor stress relief layer to a stress relief layer comprising a stress relief material that relieves stress between said substrate and said cap layer arising from differences in said first and second TECs at a growth temperature at which layers are grown epitaxially on said first semiconductor layer, said stress relief material being non-crystalline at said growth temperature.

11. The method of claim 10 wherein precursor stress relief layer comprises a material from the GaN family of materials that is converted to said stress relief material.

12. The method of claim 11 wherein said precursor material is converted to said stress relief material by heating said precursor material.

13. The method of claim 10 wherein said precursor material comprises InGaN and wherein said stress relief material comprises an alloy of In and Ga, said alloy being in a liquid state at said growth temperature.

14. The method of claim 10 further comprising epitaxially growing a light emitting device on said first semiconductor layer.

15. The method of claim 14 wherein said light emitting device has a TEC substantially equal to said second TEC.

16. The method of claim 14 wherein said light emitting device is a GaN LED and wherein said substrate comprises a silicon wafer.

17. The method of claim 16 further comprising removing said silicon wafer by heating said semiconductor device to a temperature at which said stress relief layer is in a liquid state.