SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME

• US 20120319291A1
• Filed: 06/15/2011
• Published: 12/20/2012
• Est. Priority Date: 06/15/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHIOU, Wen-Chih, WU, Tsang-Jiuh, YANG, Ku-Feng, CHEN, Hsin-Yu
• Granted Patent: US 8,587,127 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure includes a dielectric layer disposed over a substrate. A metallic line is disposed in the dielectric layer. A through-silicon-via (TSV) structure continuously extends through the dielectric layer and the substrate. A surface of the metallic line is substantially leveled with a surface of the TSV structure.

Claims

1. A semiconductor structure comprising:

a dielectric layer disposed over a substrate;

a metallic line disposed in the dielectric layer; and

a through-silicon-via (TSV) structure continuously extending through the dielectric layer and the substrate, wherein a surface of the metallic line is substantially level with a surface of the TSV structure.

2. The semiconductor structure of claim 1, wherein a surface of the dielectric layer is substantially level with the surface of the TSV structure.

3. The semiconductor structure of claim 1, further comprising:

at least one contact plug that is electrically coupled between the metallic line and a transistor that is disposed over the substrate.

4. The semiconductor structure of claim 3, wherein the TSV structure is continuous at a region that is substantially level with an interface between the at least one contact plug and the metallic line.

5. The semiconductor structure of claim 1, wherein the dielectric layer continuously extends between the TSV structure and the substrate.

6. The semiconductor structure of claim 5, wherein a first portion of the dielectric layer that is between the TSV structure and the substrate is thicker than a second portion of the dielectric layer that is over the substrate.

7. The semiconductor structure of claim 1, wherein the semiconductor structure is an interposer and the metallic line is a portion of a redistribution layer (RDL) of the interposer.

8. A semiconductor structure comprising:

a through-silicon-via (TSV) structure continuously extending through a substrate;

a liner layer continuously extending over the substrate and between the TSV structure and the substrate, wherein a surface of the liner layer is substantially level with a surface of the TSV structure; and

a metallic line disposed in the liner layer.

9. The semiconductor structure of claim 8, wherein a surface of the metallic line is substantially level with the surface of the TSV structure.

10. The semiconductor structure of claim 8, further comprising:

at least one contact plug that is electrically coupled between the metallic line and a transistor that is disposed over the substrate.

11. The semiconductor structure of claim 10, wherein the TSV structure is continuous at a region that is substantially level with an interface between the at least one contact plug and the metallic line.

12. The semiconductor structure of claim 8, wherein a first portion of the liner layer that is between the TSV structure and the substrate is thicker than a second portion of the liner layer that is over the substrate.

13. The semiconductor structure of claim 8, wherein the semiconductor structure is an interposer and the metallic line is a portion of a redistribution layer (RDL) of the interposer.

14. A method of forming a semiconductor structure, the method comprising:

forming a through-silicon-via (TSV) opening in a substrate;

forming a dielectric layer continuously extending over the substrate and into the TSV opening;

forming at least one conductive material over the dielectric layer and in the TSV opening;

removing a portion of the at least one conductive material that is over the dielectric layer to form a TSV structure in the substrate;

forming a metallic line in the dielectric layer; and

removing a portion of the substrate, such that the TSV structure continuously extends through the substrate and the dielectric layer.

15. The method of claim 14, wherein forming the metallic line comprises:

forming a cap layer over the dielectric layer;

forming a patterned mask layer over the cap layer, the patterned mask layer covering the TSV structure and exposing a portion of the cap layer;

removing the exposed portion of the cap layer and a portion of the dielectric layer by using the patterned mask layer as an etch mask to form an opening in the dielectric layer;

removing the patterned mask layer; and

forming the metallic line in the opening in the dielectric layer.

16. The method of claim 15, wherein forming the metallic line in the opening in the dielectric layer comprises

forming at least one metallic material over the cap layer and in the opening in the dielectric layer;

and

removing a portion of the at least one metallic material that is over the dielectric layer by a chemical mechanical polish (CMP) process to form the metallic line in the opening in the dielectric layer, wherein a surface of the TSV structure is substantially leveled with a surface of the metallic line.

17. The method of claim 15, wherein the cap layer is provided to protect the TSV structure from being oxidized by the patterned mask layer.

18. The method of claim 14, further comprising:

forming at least one transistor over the substrate; and

forming at least one contact plug that is electrically coupled between the metallic line and the at least one transistor, wherein a surface of the dielectric layer is substantially leveled with the surface of the TSV structure.

19. The method of claim 18, wherein the TSV structure does not have an interface at a region that is substantially leveled with an interface between the at least one contact plug and the metallic line.