INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF

• US 20120319295A1
• Filed: 06/17/2011
• Published: 12/20/2012
• Est. Priority Date: 06/17/2011
• Status: Abandoned Application

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Chi, HeeJo, Cho, NamJu, Shin, HanGil
• Time in patent office: 0 Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24101 Connecting bonding areas at the same height
• CPC Class Codes: H01L 2224/24147 the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/26 : Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a circuit structure having a circuit active side and a cavity from the circuit active side; mounting an integrated circuit device in the cavity; forming a base encapsulation, having a base first side facing away from the circuit active side, on the circuit active side, around the integrated circuit device, and in the cavity; forming a first conductive pin, having a first pin height, in the base encapsulation and traversing from the circuit active side to the base first side; forming a second conductive pin, having a second pin height equivalent to the first pin height, in the base encapsulation and traversing from the integrated circuit device to the base first side; and removing a portion of the circuit structure to form a circuit non-active side and expose the integrated circuit device and a base second side.

Claims

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a circuit structure having a circuit active side and a cavity from the circuit active side;

mounting an integrated circuit device in the cavity;

forming a base encapsulation, having a base first side facing away from the circuit active side, on the circuit active side, around the integrated circuit device, and in the cavity;

forming a first conductive pin, having a first pin height, in the base encapsulation and traversing from the circuit active side to the base first side;

forming a second conductive pin, having a second pin height equivalent to the first pin height, in the base encapsulation and traversing from the integrated circuit device to the base first side; and

removing a portion of the circuit structure to form a circuit non-active side and expose the integrated circuit device and a base second side, the base second side opposite the base first side.

2. The method as claimed in claim 1 further comprising forming a through pin, adjacent to the circuit structure, in the base encapsulation and traversing from the base first side to the base second side.

3. The method as claimed in claim 1 wherein forming the circuit structure includes forming a conductive via, in the circuit structure, traversing from the circuit active side to the circuit non-active side.

4. The method as claimed in claim 1 wherein removing the portion of the circuit structure includes forming a through hole traversing from the circuit active side and the circuit non-active side.

5. The method as claimed in claim 1 further comprising mounting a mountable device on the base first side of the base encapsulation.

6. A method of manufacture of an integrated circuit packaging system comprising:

forming a circuit structure having a circuit active side and a cavity from the circuit active side;

mounting an integrated circuit device, having a device active side, in the cavity;

forming a base encapsulation, having a base first side facing away from the circuit active side and a base second side opposite the base first side, on the circuit active side, around the integrated circuit device, and in the cavity;

forming a first conductive pin, having a first pin height, in the base encapsulation traversing from the circuit active side to and co-planar with the base first side;

forming a second conductive pin, having a second pin height equivalent to the first pin height, in the base encapsulation traversing from the device active side to and co-planar with the base first side; and

removing a portion of the circuit structure to form a circuit non-active side, a device non-active side of the integrated circuit device, and expose a base second side.

7. The method as claimed in claim 6 wherein forming the first conductive pin includes connecting the first conductive pin with a conductive via in the circuit structure.

8. The method as claimed in claim 6 further comprising:

mounting an internal integrated circuit on the device active side of the integrated circuit device; and

wherein forming the base encapsulation includes covering the internal integrated circuit.

9. The method as claimed in claim 6 further comprising mounting a component device on the circuit active side of the circuit structure.

10. The method as claimed in claim 6 wherein the circuit non-active side and the device non-active side are exposed from the base encapsulation and co-planar with the base second side.

11. An integrated circuit packaging system comprising:

a circuit structure having a through hole, a circuit active side, and a circuit non-active side with the through hole traversing from the circuit active side to the circuit non-active side;

an integrated circuit device in the through hole;

a base encapsulation, having a base first side facing away from the circuit active side and a base second side opposite the base first side, on the circuit active side, around the integrated circuit device, and in the through hole;

a first conductive pin, having a first pin height, in the base encapsulation and traversing from the circuit active side to the base first side; and

a second conductive pin, having a second pin height equivalent to the first pin height, in the base encapsulation and traversing from the integrated circuit device to the base first side.

12. The system as claimed in claim 11 further comprising a through pin, adjacent to the circuit structure, in the base encapsulation and traversing from the base first side to the base second side.

13. The system as claimed in claim 11 further comprising a conductive via in the circuit structure and traversing from the circuit active side to the circuit non-active side.

14. The system as claimed in claim 11 further comprising a conductive trace connecting the first conductive pin and the second conductive pin.

15. The system as claimed in claim 11 further comprising a mountable device on the base first side of the base encapsulation.

16. The system as claimed in claim 11 wherein:

the integrated circuit device includes a device active side and a device non-active side;

and the second conductive pin traverses from the device active side to the base first side.

17. The system as claimed in claim 16 wherein the first conductive pin is connected with a conductive via in the circuit structure.

18. The system as claimed in claim 16 further comprising:

an internal integrated circuit on the device active side of the integrated circuit device; and

wherein the base encapsulation covers the internal integrated circuit.

19. The system as claimed in claim 16 further comprising a component device on the circuit active side of the circuit structure.

20. The system as claimed in claim 16 wherein the circuit non-active side and the device non-active side are exposed from the base encapsulation and co-planar with the base second side.