SYSTEM FOR PROCESSING DATA STREAMS

• US 20120319885A1
• Filed: 06/17/2012
• Published: 12/20/2012
• Est. Priority Date: 06/16/2011
• Status: Active Grant

• Current Assignee: Spatial Digital Systems Inc
• Original Assignee: Spatial Digital Systems Inc
• Inventors: Chang, Donald C. D.
• Granted Patent: US 8,953,728 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3258 based on polynomial terms
• CPC Class Codes: H03F 2201/3212 Using a control circuit to adjust amplitude and phase of a signal in a signal path
• CPC Class Codes: H03F 2203/21106 An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 2203/21109 An input signal being distributed by switching to a plurality of paralleled power amplifiers
• CPC Class Codes: H03F 2203/21136 An input signal of a power amplifier being on/off switched
• CPC Class Codes: H03F 2203/21145 Output signals are combined by switching a plurality of paralleled power amplifiers to a common output
• CPC Class Codes: H03F 2203/21175 An output signal of a power amplifier being on/off switched
• CPC Class Codes: H03F 2203/7215 the gated amplifier being switched on or off by a switch at the input of the amplifier
• CPC Class Codes: H03F 2203/7224 the gated amplifier being switched on or off by clamping by a switch at the output of the amplifier
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H04B 7/18515 Transmission equipment in satellites or space-based relays

Abstract

A system for processing data streams or signals includes a wave-front multiplexer configured to process first and second input signals into first and second output signals each carrying information associated with the first and second input signals, a first processing unit configured to process a third input signal carrying information associated with the first output signal into a third output signal, a second processing unit configured to process a fourth input signal carrying information associated with the second output signal into a fourth output signal, and a wave-front demultiplexer configured to process fifth and sixth input signals into fifth and sixth output signals each carrying information associated with the fifth and sixth input signals. The fifth input signal carries information associated with the third output signal, and the sixth input signal carries information associated with the fourth output signal.

Claims

1. A method for processing data streams comprising:

passing a first analog signal through a first channel;

passing a second analog signal through a second channel parallel to said first channel;

passing a third analog signal through a third channel, wherein said third analog signal carries information associated with said first and second analog signals;

passing a fourth analog signal through a fourth channel parallel to said third channel, wherein said fourth analog signal carries information associated with said first and second analog signals;

performing a first analog-to-digital conversion to convert said third analog signal into a first digital signal;

performing a second analog-to-digital conversion to convert said fourth analog signal into a second digital signal;

passing a third digital signal through a fifth channel, wherein said third digital signal carries information associated with said first and second digital signals; and

passing a fourth digital signal through a sixth channel parallel to said fifth channel, wherein said fourth digital signal carries information associated with said first and second digital signals.

2. The method of claim 1, wherein said third digital signal substantially equals digital representation of said first analog signal, and said fourth digital signal substantially equals digital representation of said second analog signal.

3. The method of claim 1, wherein said third digital signal substantially equals digital representation of said first analog signal multiplied by a multiplier, and said fourth digital signal substantially equals digital representation of said second analog signal multiplied by said multiplier.

4. The method of claim 1 further comprising passing a fifth analog signal through a seventh channel parallel to said first and second channels, passing a sixth analog signal through an eighth channel parallel to said third and fourth channels, wherein said sixth analog signal carries information associated with said first, second and fifth analog signals, wherein said third analog signal further carries information associated with said fifth analog signal, wherein said fourth analog signal further carries information associated with said fifth analog signal, performing a third analog-to-digital conversion to convert said sixth analog signal into a fifth digital signal, and passing a sixth digital signal through a ninth channel parallel to said fifth and sixth channels, wherein said sixth digital signal carries information associated with said first, second and fifth digital signals, wherein said third digital signal further carries information associated with said fifth digital signal, wherein said fourth digital signal further carries information associated with said fifth digital signal.

5. The method of claim 1, wherein said second analog signal comprises a ground voltage.

6. The method of claim 1, before said passing said third and fourth digital signals, further comprising multiplying said second digital signal by a multiplier.

7. The method of claim 6 further comprising calculating a difference between said fourth digital signal and a predetermined value, wherein said second analog signal comprises said predetermined value, calculating a correlation between said third and fourth digital signals, calculating a summed value by performing a weighted summation of said difference and said correlation, calculating a variation in said summed value, and adjusting said multiplier based on said variation.

8. The method of claim 1, wherein said performing said first analog-to-digital conversion is based on the same sampling frequency as said performing said second analog-to-digital conversion.

9. The method of claim 1, wherein said performing said first analog-to-digital conversion is based on the same analog-to-digital conversion resolution as said performing said second analog-to-digital conversion.

10. The method of claim 1, wherein said first analog signal is attenuated at a part thereof with a frequency higher than a cutoff frequency.

11. The method of claim 1, wherein said third and fourth analog signals are processed by a first orthogonal matrix multiplied by a matrix comprising said first and second analog signals, wherein said third and fourth digital signals are processed by a second orthogonal matrix multiplied by a matrix comprising said first and second digital signals.

12. The method of claim 11, wherein said first and second orthogonal matrices comprise Butler matrices.

13. The method of claim 11, wherein said first and second orthogonal matrices comprise Hadamard matrices.

14. The method of claim 1, wherein said third analog signal further carries information associated with a first sum of said first analog signal multiplied by a first multiplier plus said second analog signal multiplied by a second multiplier, wherein said fourth analog signal further carries information associated with a second sum of said first analog signal multiplied by a third multiplier plus said second analog signal multiplied by a fourth multiplier, wherein said third digital signal further carries information associated with a third sum of said first digital signal multiplied by a fifth multiplier plus said second digital signal multiplied by a sixth multiplier, and wherein said fourth digital signal further carries information associated with a fourth sum of said first digital signal multiplied by a seventh multiplier plus said second digital signal multiplied by an eighth multiplier.

15. The method of claim 14, wherein said first multiplier substantially equals said fifth multiplier, said second multiplier substantially equals said sixth multiplier, said third multiplier substantially equals said seventh multiplier, and said fourth multiplier substantially equals said eighth multiplier.

16. The method of claim 14, wherein said first multiplier substantially equals the conjugate of said fifth multiplier, said second multiplier substantially equals the conjugate of said sixth multiplier, said third multiplier substantially equals the conjugate of said seventh multiplier, said fourth multiplier substantially equals the conjugate of said eighth multiplier.

17. The method of claim 1, before said passing said third analog signal, further comprising passing a fifth analog signal through a wireless channel sequential to said third channel, wherein said fifth analog signal carries information associated with aid first and second analog signals.

18. A system for processing data streams comprising:

a first processor configured to receive a first analog signal from a first input port of said first processor and receive a second analog signal from a second input port of said first processor parallel to said first input port of said first processor;

a first analog-to-digital converter configured to receive a third analog signal from a first input port of said first analog-to-digital converter, wherein said third analog signal carries information associated with said first and second analog signals, perform a first analog-to-digital conversion to convert said third analog signal into a first digital signal, and output said first digital signal from a first output port of said first analog-to-digital converter;

a second analog-to-digital converter configured to receive a fourth analog signal from an input port of said second analog-to-digital converter, wherein said fourth analog signal carries information associated with said first and second analog signals, perform a second analog-to-digital conversion to convert said fourth analog signal into a second digital signal and output said second digital signal from an output port of said second analog-to-digital converter; and

a second processor configured to output a third digital signal from a first output port of said second processor, wherein said third digital signal carries information associated with said first and second digital signals, and output a fourth digital signal from a second output port of said second processor parallel to said first output port of said second processor, wherein said fourth digital signal carries information associated with said first and second digital signals.

19. The system of claim 18 further comprising an equalizer at said second output port of said second processor, wherein said equalizer is configured to multiply said second digital signal by a multiplier.

20. The system of claim 19, further comprising an optimizer at said second output port of said second processor, wherein said optimizer is configured to calculate a difference between said fourth digital signal and a predetermined value, wherein said second analog signal comprises said predetermined value, calculate a correlation between said third and fourth digital signals, calculate a summed value by performing a weighted summation of said difference and said correlation, and calculate a variation in said summed value, wherein said multiplier is configured to be adjusted based on said variation.