NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ERASING DATA THEREOF

• US 20120320698A1
• Filed: 06/11/2012
• Published: 12/20/2012
• Est. Priority Date: 06/14/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: ITAGAKI, Kiyotaro, IWATA, Yoshihisa, YAMADA, Kunihiro
• Granted Patent: US 8,817,538 B2
• Time in Patent Office: Days
• US Class Current: 365/218
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a memory cell array comprising a memory string including a plurality of memory cells, the memory cells being stacked on the semiconductor substrate;

a plurality of word lines connected to the plurality of memory cells;

a bit line electrically connected to one end of the memory string;

a source line electrically connected to the other end of the memory string;

a drain-side select transistor provided between one end of the memory string and the bit line;

a source-side select transistor provided between the other end of the memory string and the source line; and

a control circuit configured to control voltages to be applied to the memory string, the plurality of word lines, the bit line, and the source line, and

the control circuit being configured to set the drain-side select transistor and the source-side select transistor connected to a selected memory string to non-conductive states, the control circuit being configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string, the control circuit being configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string, the second voltage being smaller than the first voltage in an erasing operation.

2. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a drain-side select gate line connected to a gate of the drain-side select transistor; and

a source-side select gate line connected to a gate of the source-side select transistor,

wherein, in the selected memory string, the control circuit gives third voltages to the bit line and the source line and gives fourth voltages to the drain-side select gate line and the source-side select gate line,

in a first non-selected memory string connected to the bit line and the source line in common with the selected memory string, the control circuit gives fifth voltages to the drain-side select gate line and the source-side select gate line in a case where a voltage of the semiconductor layer of the first non-selected memory string is raised to a sixth voltage or higher, each of the fifth voltages being larger by a first value than the fourth voltage, and

in a second non-selected memory string connected to the drain-side select gate line, the source-side select gate line, and the source line in common with the selected memory string, the control circuit gives a seventh voltage to the bit line in a case where a voltage of the semiconductor layer of the second non-select memory string is raised to a eighth voltage or higher, the seventh voltage being smaller by a second value than the third voltage.

3. The nonvolatile semiconductor memory device according to claim 2, wherein the third voltage is set to a value that prevents data held in a memory cell from being changed when the third voltage is applied to the semiconductor layer, and the first voltage is applied to the non-selected word line.

4. The nonvolatile semiconductor memory device according to claim 2, wherein the third voltage is set to a value that prevents data held in a memory cell from being changed when the third voltage is applied to the semiconductor layer, and the second voltage is applied to the selected word line.

5. The nonvolatile semiconductor memory device according to claim 3, wherein the third voltage is set to a value that prevents data held in a memory cell from being changed when the third voltage is applied to the semiconductor layer, and when the second voltage is applied to the selected word line.

6. The nonvolatile semiconductor memory device according to claim 1, wherein the erasing operation comprises a soft-erasing operation performed after a writing operation.

7. The nonvolatile semiconductor memory device according to claim 1, wherein the control circuit raises a voltage of the non-selected word line to the first voltage in several batches.

8. The nonvolatile semiconductor memory device according to claim 2, wherein the first voltage and the fifth voltage are positive voltages, the second voltage and the seventh voltage are negative voltages, and the third voltage and the fourth voltage are ground voltages.

9. The nonvolatile semiconductor memory device according to claim 2, wherein the first voltage, the third voltage, the fourth voltage, the fifth voltage, and the seventh voltage are positive voltages, and the second voltage is a ground voltage.

10. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell comprises:

the first semiconductor layer;

a charge accumulation layer provided on a side surface of the first semiconductor layer and enabling accumulation of charges; and

a first conductive layer provided on a side surface of the first semiconductor layer via the charge accumulation layer and functioning as a gate of the memory cell and the word line.

11. A method for erasing data of a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including:

a semiconductor substrate;

a memory cell array comprising a memory string comprising a plurality of memory cells, the memory cells being stacked on the semiconductor substrate;

a plurality of word lines connected to the plurality of memory cells;

a bit line electrically connected to one end of the memory string;

a source line electrically connected to the other end of the memory string;

a drain-side select transistor provided between one end of the memory string and the bit line; and

a source-side select transistor provided between the other end of the memory string and the source line,

the method comprising setting the drain-side select transistor and the source-side select transistor connected to a selected memory string to non-conductive states, applying a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string, and applying a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string, the second voltage being smaller than the first voltage in an erasing operation.

12. The method for erasing data of a nonvolatile semiconductor memory device according to claim 11, the nonvolatile semiconductor memory device further including:

a drain-side select gate line connected to a gate of the drain-side select transistor; and

a source-side select gate line connected to a gate of the source-side select transistor,

wherein, in the selected memory string, the method gives third voltages to the bit line and the source line and gives fourth voltages to the drain-side select gate line and the source-side select gate line,

in a first non-selected memory string connected to the bit line and the source line in common with the selected memory string, the method gives fifth voltages to the drain-side select gate line and the source-side select gate line in a case where a voltage of the semiconductor layer of the first non-selected memory string is raised to a sixth voltage or higher, each of the fifth voltages being larger by a first value than the fourth voltage, and

in a second non-selected memory string connected to the drain-side select gate line, the source-side select gate line, and the source line in common with the selected memory string, the method gives a seventh voltage to the bit line in a case where a voltage of the semiconductor layer of the second non-selected memory string is raised to a eighth voltage or higher, the seventh voltage being smaller by a second value than the third voltage.

13. The method for erasing data of a nonvolatile semiconductor memory device according to claim 12, wherein the third voltage is set to a value that prevents data held in a memory cell from being changed when the third voltage is applied to the semiconductor layer, and the first voltage is applied to the non-selected word line.

14. The method for erasing data of a nonvolatile semiconductor memory device according to claim 12, wherein the third voltage is set to a value that prevents data held in a memory cell from being changed when the third voltage is applied to the semiconductor layer, and the second voltage is applied to the selected word line.

15. The method for erasing data of a nonvolatile semiconductor memory device according to claim 13, wherein the third voltage is set to a value that prevents data held in a memory cell from being changed when the third voltage is applied to the semiconductor layer, and the second voltage is applied to the selected word line.

16. The method for erasing data of a nonvolatile semiconductor memory device according to claim 11, wherein the erasing operation includes a soft-erasing operation performed after a writing operation.

17. The method for erasing data of a nonvolatile semiconductor memory device according to claim 11, wherein a voltage of the non-selected word line is raised to the first voltage in several batches.