Non-Real-Time Dither Using a Programmable Matrix

• US 20130002703A1
• Filed: 09/21/2011
• Published: 01/03/2013
• Est. Priority Date: 06/28/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Tripathi, Brijesh, Okruhlica, Craig M., Roethig, Wolfgang
• Granted Patent: US 8,963,946 B2
• Time in Patent Office: Days
• US Class Current: 345/596
• CPC Class Codes: G09G 2320/0271 Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
• CPC Class Codes: G09G 3/2051 with use of a spatial dither pattern
• CPC Class Codes: G09G 5/04 using circuits for interfacing with colour displays

Abstract

A dither unit with a programmable kernel matrix in which each indexed location/entry may store one or more dither values. Each dither value in a respective entry of the kernel matrix may correspond to the number of bits that are truncated during dithering. During dithering of each pixel of an image, entries in the kernel matrix may be indexed according to the relative coordinates of the pixel within the image. A dither value for the pixel may be selected from the indexed entry based on the truncated least significant bits of the pixel component value. When the kernel matrix is storing more than one dither value per entry, the dither value may be selected based further on the number of truncated least significant bits. A dithered pixel component value may then be generated according to the dither value and the remaining most significant bits of the pixel component value.

Claims

1. A dither unit comprising:

a dither control circuit comprising a programmable dither kernel matrix, the dither control circuit configured to;

receive one or more least significant bits of a pixel component value corresponding to a pixel of an image;

receive at least a portion of horizontal and vertical coordinates indicative of a relative position of the pixel within the image;

receive an indication of a specific number of least significant bits to be truncated from the pixel component value;

truncate the one or more least significant bits from the pixel component value according to the specific number; and

generate a dither kernel value responsive to the programmable dither kernel matrix, the one or more least significant bits of the pixel component value, the specific number, and the at least a portion of the horizontal and vertical coordinates; and

an adder coupled to receive the dither kernel value and a plurality of most significant bits of the pixel component value, wherein the plurality of most significant bits exclude the specific number of least significant bits of the pixel component value, and wherein the adder is configured to add the dither kernel value to the most significant bits of the pixel value to generate a dithered output pixel value.

2. The dither unit of claim 1, further comprising a separator unit configured to receive the pixel component value, and separate the pixel component value into the one or more least significant bits and the plurality of most significant bits of the pixel component value.

3. The dither unit of claim 1, wherein the dither control circuit is configured to:

index an entry in the dither kernel matrix according to the at least a portion of the horizontal and vertical coordinates; and

select a value stored at the indexed entry to generate the dither kernel value.

4. The dither unit of claim 3, wherein the dither control circuit is configured to select the value stored at the indexed entry according to the one or more least significant bits of the pixel component value.

5. The dither unit of claim 3, wherein the dither kernel matrix is configured to store two or more values at each entry, and wherein the dither control circuit is configured to select the value stored at the indexed entry according to the specific number and the one or more least significant bits of the pixel component value.

6. A method for dithering, the method comprising:

receiving a first number of least significant bits (LSBs) of a pixel component value corresponding to a pixel of an image;

receiving at least a portion of horizontal and vertical coordinates indicative of a position of the pixel within the image;

receiving a second number indicative of a number of least significant bits to be truncated from the pixel component value;

receiving a third number of most significant bits (MSBs) of the pixel component value;

retrieving a dither value from a programmable dither kernel matrix according to the at least a portion of horizontal and vertical coordinates, the second number, and the first number of LSBs; and

generating a dithered output pixel component value from the third number of MSBs and the retrieved dither value.

7. The method of claim 6, wherein generating the dithered output pixel component value comprises:

comparing the first number of LSBs with the retrieved dither value; and

performing an arithmetic operation on the third number of MSBs responsive to results of the comparing of the first number of LSBs with the retrieved dither value;

outputting a result of the arithmetic operation as the dithered output value.

8. The method of claim 7, wherein performing the arithmetic operation on the third number of MSBs comprises:

adding a binary value of ‘

1’

to the MSBs in response to the comparing indicating that the first number of LSBs is greater than the retrieved dither value.

9. The method of claim 7, wherein performing the arithmetic operation on the third number of MSBs comprises:

adding a binary value of ‘

0’

to the MSBs in response to the comparing indicating that the first number of LSBs is less than or equal to the retrieved dither value.

10. The method of claim 6, wherein retrieving the dither value from the programmable dither kernel matrix comprises selecting one from a plurality of stored dither values according to the second number, wherein the plurality of stored dither values correspond to the at least a portion of horizontal and vertical coordinates.

11. A system comprising:

a memory element configured to store images comprising pixels, each pixel of the pixels represented by pixel component values in a specified color space;

a non-real-time (NRT) peripheral unit comprising a programmable kernel matrix, and configured to;

communicate with the memory element to retrieve the stored images;

for each retrieved pixel of the retrieved stored images;

retrieve a dither value from the programmable kernel matrix according to relative coordinates of the retrieved pixel within the image, a first number of least significant bits (LSBs) of a color component value of the retrieved pixel, and the first number; and

generate a dithered color component value of the retrieved pixel based on the retrieved dither value and a second number of most significant bits (MSBs) of the color component value of the retrieved pixel, to generate dithered pixels to represent a dithered image; and

store the dithered image in the memory element.

12. The system of claim 11, wherein in retrieving the dither value from the programmable kernel matrix, the NRT peripheral unit is configured to index the programmable kernel matrix according to the relative coordinates of the retrieved pixel within the image.

13. The system of claim 11, wherein the programmable kernel matrix is configured to store a plurality of value corresponding to the relative coordinates of the retrieved pixel within the image, wherein each of the plurality of values corresponds to a different respective number indicative of a number of LSBs to be truncated from the color component value of the retrieved pixel.

14. The system of claim 11, wherein in generating the dithered color component value of the retrieved pixel, the NRT peripheral unit is configured to:

compare the first number of LSBs with the retrieved dither value;

adjust the second number of MSBs responsive to comparing the first number of LSBs with the retrieved dither value; and

output the adjusted second number of MSBs as the dithered color component value of the retrieved pixel.

15. The system of claim 11, wherein the NRT peripheral unit is further configured to:

retrieve a respective dither value for each respective color component value of the retrieved pixel according to the relative coordinates of the retrieved pixel within the image, a respective number of least significant bits (LSBs) of the respective color component value of the retrieved pixel, and the respective number; and

generate a dithered respective color component value of the retrieved pixel based on the retrieved respective dither value and a respective number of most significant bits (MSBs) of the respective color component value of the retrieved pixel, to generate dithered pixels to represent the dithered image.

16. The system of claim 11, wherein the color component value is representative of one of:

an RGB color space; and

a YCbCr color space.

17. A method comprising:

programming a dither kernel matrix (DKM) with a plurality of values in each indexed entry of the DKM, wherein each of the plurality of values stored in a respective indexed entry corresponds to a specific number indicative of a number of least significant bits (LSBs) to be truncated from a pixel component value during dithering;

indexing a respective entry of the DKM according to coordinates indicative of a relative position of a respective pixel within an image of which the respective pixel is a part;

specifying a first number indicative of a number of LSBs to be truncated from the pixel component value of the respective pixel for dithering;

comparing the first number of LSBs of the pixel component value of the respective pixel with a value corresponding to the first number and stored in the indexed respective entry; and

generating a dithered pixel component value of the respective pixel responsive to comparing the first number of LSBs with the value corresponding to the first number and stored in the indexed respective entry.

18. The method of claim 17, wherein generating the dithered pixel value comprises:

splitting the pixel component value into the first number of LSBs and a second number of most significant bits (MSBs);

adjusting the second number of MSBs responsive to comparing the first number of LSBs with the value corresponding to the first number and stored in the indexed respective entry; and

outputting the adjusted second number of MSBs as the dithered pixel component value.

19. The method of claim 18, wherein adjusting the second number of MSBs comprises:

adding a binary value of ‘

1’

to the second number of MSBs responsive to the first number of LSBs representing a value larger than the value corresponding to the first number and stored in the indexed respective entry; and

leaving a value represented by the second number of MSBs unchanged responsive to the first number of LSBs representing a value less than or equal to the value corresponding to the first number and stored in the indexed respective entry.

20. The method of claim 18, wherein leaving the second number of MSBs unchanged comprises adding a binary value of ‘

0’

to the second number of MSBs.

21. A system comprising:

a memory element configured to store images comprising pixels, each pixel of the pixels represented by pixel component values in a specified color space;

a programmable dither kernel matrix (DKM) configured to store a value in each entry of the DKM, wherein each stored value corresponds to a same number indicative of a specified number of least significant bits (LSBs) to be truncated from a pixel component value during dithering;

a circuit coupled to the memory element and to the programmable DKM to perform dithering, wherein in performing dithering the circuit is configured to;

receive a pixel component value corresponding to a pixel of an image and comprising the specified number of LSBs and a specified number of most significant bits (MSBs);

receive at least a portion of horizontal and vertical coordinates indicative of a relative position of the pixel within the image;

identify a respective entry in the DKM responsive to the at least a portion of horizontal and vertical coordinates;

generate a dither kernel value responsive to the specified number of LSBs and the value stored in the identified respective entry of the DKM; and

output a dithered pixel component value responsive to the dither kernel value and the specified number of MSBs.

22. The system of claim 21, wherein the circuit comprises:

an adder configured to add the dither kernel value to the specified number of MSBs to generate the dithered pixel component value.

23. The system of claim 21, further comprising a non-real-time (NRT) scaler/rotator circuit coupled to the memory element to receive images from the memory element, scale/rotate the received images, and store the scaled/rotated images in the memory element;

wherein the programmable DKM and the circuit are comprised in the NRT scaler/rotator, wherein the circuit is configured to perform dithering as part of scaling/rotating the images.