TRANSITION DETECTOR

• US 20130003905A1
• Filed: 06/30/2011
• Published: 01/03/2013
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: CHATTERJEE, Kallol, JAIN, Abhishek, PARTHASARATHY, Chittoor, SINGH, Saurabh Kumar
• Granted Patent: US 9,444,440 B2
• Time in Patent Office: Days
• US Class Current: 375/360
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.

Claims

1. A transition detector, comprising:

clock-pulse-generation circuitry configured to generate a clock pulse in response to a clock signal; and

data-pulse-generation circuitry configured to generate a data pulse in response to a transition of a data signal, the data-pulse-generation circuitry comprising delay circuitry configured to delay the generation of the data pulse such that the data pulse overlaps the clock pulse when a transition of the data signal occurs within a time window of the clock signal.

2. The transition detector of claim 1 wherein the delay circuitry is configured to delay the data signal by a first programmable delay, the data pulse being generated in response to the delayed data signal.

3. The transition detector of claim 2 wherein the first programmable delay is configured to correspond to a time difference between a start of the time window and a clock edge of the clock signal.

4. The transition detector of claim 1 wherein the clock generation circuitry is configured to generate the clock pulse having a pulse width corresponding to a second programmable delay.

5. The transition detector of claim 4 wherein the clock second programmable delay corresponds to a width of the clock window.

6. The transition detector of claim 1 wherein the clock generation circuitry is configured to generate the clock pulse responsive to a clock edge of the clock signal.

7. The transition detector of claim 1 wherein the transition detector is configured to have a self-test mode in which the data pulse generation circuitry is configured to generate the data pulse in response to a transition of the clock signal.

8. The transition detector of claim 7 further comprising a multiplexer configured to select the self-test mode.

9. The transition detector of claim 1 configured to assert a flag if the clock pulse and the data pulse overlap.

10. The transition detector of claim 9 configured to assert the flag until the transition detector is reset.

11. A method comprising:

generating a clock pulse in response to a clock signal; and

generating a data pulse in response to a transition of a data signal, said generating the data pulse comprising delaying the generation of the data pulse such that the data pulse overlaps the clock pulse when a transition of the data signal occurs within a time window of the clock signal.

12. The method of claim 11 further comprising:

detecting a transition of a data signal within the time window if the clock pulse and the data pulse overlap.

13. The method of claim 11 further comprises:

delaying the data signal by a first programmable delay and generating the data pulse in response to the delayed data signal.

14. The method of claim 13 wherein delaying the data signal by a first programmable delay comprises delaying the data signal by a time difference between a start of the time window and a clock edge of the clock signal.

15. The method of claim 11 comprising generating the clock pulse having a pulse width corresponding to a second programmable delay.

16. The method of claim 15 wherein the second programmable delay corresponds to a width of the clock window.

17. The method of claim 11 wherein generating the clock pulse comprises generating the clock pulse responsive to a clock edge of the clock signal.

18. The method of claim 16 further comprising:

generating a data pulse in response to a transition of the clock signal transition detector in accordance with a self-test mode of operation.

19. The method of claim 18 further comprising:

selecting the self test mode of operation.

20. The method of claim 11 further comprising:

asserting a flag if the clock pulse and the data pulse overlap.

21. A transition detector, comprising:

Clock-pulse-generation means for generating a clock pulse in response to a clock signal; and

data-pulse-generation means for generating a data pulse in response to a transition of a data signal, the data-pulse-generation means comprising delay means for delaying the generation of the data pulse such that the data pulse overlaps the clock pulse when a transition of the data signal occurs within a time window of the clock signal.

22. An integrated circuit comprising a transition detector, the transition detector comprising:

clock-pulse-generation circuitry configured to generate a clock pulse in response to a clock signal; and

data-pulse-generation circuitry configured to generate a data pulse in response to a transition of a data signal, the data-pulse-generation circuitry comprising delay circuitry configured to delay the generation of the data pulse such that the data pulse overlaps the clock pulse when a transition of the data signal occurs within a time window of the clock signal.

23. An integrated circuit comprising:

embedded logic and at least one critical path endpoint; and

at least one transition detector associated with a critical path endpoint, the transition detector including;

clock-pulse-generation circuitry configured to generate a clock pulse in response to a clock signal;

data-pulse-generation circuitry configured to generate a data pulse in response to a transition of a data signal, the data-pulse-generation circuitry comprising delay circuitry configured to delay the generation of the data pulse such that the data pulse overlaps the clock pulse when a transition of the data signal occurs within a time window of the clock signal.

24. A detector, comprising:

a first generator operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window; and

a second generator operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.

25. The detector of claim 24 wherein the second generator is operable to generate the second pulse having the relationship to the first pulse by generating the second pulse overlapping the first pulse in response to the transition of the second signal occurring approximately during the detection window.

26. The detector of claim 24 wherein the first generator includes a delay circuit operable to delay the first signal by approximately the length of the detection window.

27. The detector of claim 24 wherein the first generator includes:

a delay circuit operable to delay the first signal by approximately the length of the detection window; and

a logic gate having a first input node coupled to receive the delayed first signal from the delay circuit and having a second input node coupled to receive the first signal.

28. The detector of claim 24 wherein the first generator includes:

a delay circuit operable to delay the first signal by approximately the length of the detection window; and

a NOR gate having a first input node coupled to receive the delayed first signal from the delay circuit and having a second input node coupled to receive the first signal.

29. The detector of claim 24 wherein the second generator includes a delay circuit operable to delay the second signal by approximately a time from a beginning of the detection window to the transition of the first signal.

30. The detector of claim 24 wherein the second generator includes a shift circuit operable to shift the second signal such that a portion of the unshifted second signal that is aligned with a beginning of the detection window approximately corresponds to a portion of the shifted second signal that is aligned with the transition of the first signal.

31. The detector of claim 24 wherein the second generator includes:

a first delay circuit operable to delay the second signal by approximately a time from a beginning of the detection window to the transition of the first signal;

a second delay circuit operable to further delay the delayed second signal from the first delay circuit; and

a logic gate having a first input node coupled to receive the delayed second signal from the first delay circuit and having a second input node coupled to receive the further delayed second signal from the second delay circuit.

32. The detector of claim 24 wherein the second generator includes:

a first delay circuit operable to delay the second signal by approximately a time from a beginning of the detection window to the transition of the first signal;

a second delay circuit operable to further delay the delayed second signal from the first delay circuit; and

an XOR gate having a first input node coupled to receive the delayed second signal from the first delay circuit and having a second input node coupled to receive the further delayed second signal from the second delay circuit.

33. The detector of claim 24, further including a mode selector operable to configure the second generator to receive the first signal and to generate the second pulse in response to a transition of the first signal occurring approximately during the detection window.

34. The detector of claim 24, further including a mode selector operable to configure the second generator to receive the first signal and to generate the second pulse in response to the first transition of the first signal.

35. The detector of claim 24, further including a relationship indicator coupled to the first and second generators and operable to indicate if the second pulse has the relationship to the first pulse.

36. The detector of claim 24, further including an error indicator:

coupled to the first and second generators;

operable to detect the second pulse having the relationship to the first pulse; and

operable to indicate an error in response to detecting the second pulse having the relationship to the first pulse.

37. The detector of claim 24, further including an error indicator including:

a first logic gate coupled to receive the first and second pulses and a feedback signal, and operable to generate a first intermediate signal;

a second logic gate coupled to receive the first intermediate signal and the feedback signal and operable to generate a second intermediate signal; and

a third logic gate coupled to receive the second intermediate signal and operable to generate a relationship-indication signal.

38. The detector of claim 37 wherein the feedback signal includes the relationship-indication signal.

39. The detector of claim 37, further including a fourth logic gate coupled to receive the relationship-indication signal and operable to generate the feedback signal.

40. The detector of claim 24, further including an error indicator including:

a NAND gate coupled to receive the first and second pulses and a feedback signal, and operable to generate a first intermediate signal;

an AND gate coupled to receive the first intermediate signal and the feedback signal and operable to generate a second intermediate signal; and

a NOR gate coupled to receive the second intermediate signal and operable to generate a relationship-indication signal.

44. The integrated circuit of claim 39 wherein the detector further includes an error indicator:

coupled to the first and second generators;

operable to detect the relationship between the second and first pulses; and

operable to indicate an error in response to detecting the relationship.

41. An integrated circuit, comprising:

a detector, including

a first input node operable to receive a first signal;

a second input node operable to receive a second signal;

a first generator coupled to the first input node and operable to generate in response to a transition of the first signal a first pulse having a length that is approximately equal to a length of a detection window; and

a second generator coupled to the second input node and operable in a first mode to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.

42. The integrated circuit of claim 41 wherein the second generator is coupled to the first input node and is operable in a second mode to generate the second pulse in response to a transition of the first signal.

43. The integrated circuit of claim 41 wherein the detector further includes a relationship detector coupled to the first and second generators and operable to indicate the relationship between the second and first pulses.

47. The system of claim 43 wherein the first and second integrated circuits are disposed on respective dies.

48. The system of claim 43 wherein one of the first and second integrated circuits includes a controller.

45. A system, comprising:

a first integrated circuit, including

a detector, including

a first input node operable to receive a first signal;

a second input node operable to receive a second signal;

a first generator coupled to the first input node and operable to generate in response to a transition of the first signal a first pulse having a length that is approximately equal to a length of a detection window; and

a second generator coupled to the second input node and operable in a first mode to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window; and

a second integrated circuit coupled to the first integrated circuit.

46. The system of claim 45 wherein the first and second integrated circuits are disposed on a same die.

49. A method, comprising:

generating a first pulse having a length that is approximately equal to a length of a detection window in response to a transition of a first signal; and

generating a second pulse that has a relationship to the first pulse in response to a transition of a second signal occurring approximately during the detection window.

50. The method of claim 49, further including:

delaying the first signal by approximately the length of the detection window; and

wherein generating the first pulse includes comparing the delayed first signal to the first signal.

51. The method of claim 49, further including delaying the second signal by approximately a time from a beginning of the detection window to the transition of the first signal.

52. The method of claim 49, further including shifting a portion of the second signal that is aligned with a beginning of the detection window before the shift into approximate alignment with the transition of the first signal.

53. The method of claim 49, further including:

delaying the second signal by approximately a time from a beginning of the detection window to the transition of the first signal;

further delaying the second signal; and

wherein generating the second pulse includes comparing the delayed second signal to the further delayed second signal.

54. The method of claim 49, further including indicating that the second pulse has the relationship to the first pulse.

55. The method of claim 49, further including:

detecting that the second pulse has the relationship to the first pulse; and

indicating an error in response to detecting the relationship between the second and first pulses.

56. The method of claim 49 wherein:

the first signal includes a clock signal; and

the second signal includes a data signal.

57. A method, comprising:

generating a first pulse having a length that is approximately equal to a length of a detection window in response to a first transition of a first signal;

generating a second pulse in response to a second transition of the first signal, the second pulse having a relationship to the first pulse if the second transition of the first signal occurs approximately during the detection window.

58. The method of claim 57 wherein the first and second transitions are a same transition of the first signal.

59. The method of claim 57, further including:

wherein the first and second transitions are a same transition of the first signal; and

indicating proper operation in response to the second pulse having the relationship to the first pulse.

60. The method of claim 57, further including:

wherein the first and second transitions are a same transition of the first signal; and

indicating improper operation in response to the second pulse not having the relationship to the first pulse.