SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20130009209A1
• Filed: 06/28/2012
• Published: 01/10/2013
• Est. Priority Date: 07/08/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 9,214,474 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer.

Claims

1. A semiconductor device comprising:

an oxide semiconductor stack layer comprising a first oxide semiconductor layer and a second oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor stack layer;

a gate insulating film over the source electrode layer and the drain electrode layer; and

a gate electrode layer over the gate insulating film, the gate electrode layer overlapping with the oxide semiconductor stack layer,

wherein energy gaps of the first oxide semiconductor layer and the second oxide semiconductor layer are different from each other,

wherein, a mixed region whose composition is different from a composition of the first oxide semiconductor layer and a composition of the second oxide semiconductor layer is between the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a first element,

wherein the second oxide semiconductor layer comprises a second element, and

wherein the mixed region comprises the first element and the second element.

2. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer is formed over the first oxide semiconductor layer to cover a top surface and side surfaces of the first oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein a region of the oxide semiconductor stack layer, which does not overlap with the source electrode layer or the drain electrode layer, has higher oxygen concentration than a region overlapping with the source electrode layer and the drain electrode layer.

4. The semiconductor device according to claim 1, wherein a region of the oxide semiconductor stack layer, which does not overlap with the gate electrode layer, contains a dopant.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

6. A semiconductor device comprising:

an oxide semiconductor stack layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor stack layer;

a gate insulating film over the source electrode layer and the drain electrode layer; and

a gate electrode layer over the gate insulating film, the gate electrode layer overlapping with the oxide semiconductor stack layer,

wherein the second oxide semiconductor layer is between the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein a first mixed region whose composition is different from a composition of the first oxide semiconductor layer and a composition of the second oxide semiconductor layer is between the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein a second mixed region whose composition is different from the composition of the second oxide semiconductor layer and a composition of the third oxide semiconductor layer is between the second oxide semiconductor layer and the third oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a first element,

wherein the second oxide semiconductor layer comprises a second element,

wherein the third oxide semiconductor layer comprises a third element,

wherein the first mixed region comprises the first element and the second element, and

wherein the second mixed region comprises the second element and the third element.

7. The semiconductor device according to claim 6, wherein an electron affinity of the second oxide semiconductor layer is higher than an electron affinity of the first oxide semiconductor layer and an electron affinity of the third oxide semiconductor layer.

8. The semiconductor device according to claim 6, wherein the third oxide semiconductor layer is formed to cover side surfaces of the first oxide semiconductor layer and a top surface and side surfaces of the second oxide semiconductor layer.

9. The semiconductor device according to claim 6, wherein a region of the oxide semiconductor stack layer, which does not overlap with the source electrode layer or the drain electrode layer, has higher oxygen concentration than a region overlapping with the source electrode layer and the drain electrode layer.

10. The semiconductor device according to claim 6, wherein a region of the oxide semiconductor stack layer, which does not overlap with the gate electrode layer, contains a dopant.

11. The semiconductor device according to claim 6,

wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

12. A method for manufacturing a semiconductor device comprising the steps of:

forming, over an oxide insulating film, an oxide semiconductor stack layer comprising a first oxide semiconductor layer and a second oxide semiconductor layer with energy gaps different from each other;

forming a mixed region whose composition is different from a composition of the first oxide semiconductor layer and a composition of the second oxide semiconductor layer interposed between the first oxide semiconductor layer and the second oxide semiconductor layer by performing heat treatment on the oxide semiconductor stack layer;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor stack layer;

forming a gate insulating film covering the source electrode layer and the drain electrode layer; and

forming a gate electrode layer over the gate insulating film.

13. The method for manufacturing a semiconductor device according to claim 12, wherein hydrogen or moisture contained in the oxide semiconductor stack layer is released by the heat treatment.

14. The method for manufacturing a semiconductor device according to claim 12, wherein a dopant is added to the oxide semiconductor stack layer in a self-aligned manner using the gate electrode layer as a mask.

15. The method for manufacturing a semiconductor device according to claim 12, wherein the oxide insulating film is formed over a semiconductor substrate including a transistor.

16. The semiconductor device according to claim 12,

wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

17. A method for manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor layer over an oxide insulating film;

forming an oxide semiconductor stack layer by forming a second oxide semiconductor layer whose energy gap is larger than an energy gap of the first oxide semiconductor layer to cover a top surface and side surfaces of the first oxide semiconductor layer;

forming a mixed region whose composition is different from compositions of the first oxide semiconductor layer and the second oxide semiconductor layer interposed between the first oxide semiconductor layer and the second oxide semiconductor layer by performing heat treatment on the oxide semiconductor stack layer;

forming a source electrode layer and a drain electrode layer over the second oxide semiconductor layer;

forming a gate insulating film covering the source electrode layer and the drain electrode layer; and

forming a gate electrode layer over the gate insulating film.

18. The method for manufacturing a semiconductor device according to claim 17, wherein hydrogen or moisture contained in the oxide semiconductor stack layer is released by the heat treatment.

19. The method for manufacturing a semiconductor device according to claim 17, wherein a dopant is added to the oxide semiconductor stack layer in a self-aligned manner using the gate electrode layer as a mask.

20. The method for manufacturing a semiconductor device according to claim 17, wherein the oxide insulating film is formed over a semiconductor substrate including a transistor.

21. The semiconductor device according to claim 17,

wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

22. A method for manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor layer over an oxide insulating film;

forming, over the first oxide semiconductor layer, a second oxide semiconductor layer whose energy gap is smaller than an energy gap of the first oxide semiconductor layer;

forming an oxide semiconductor stack layer by forming a third oxide semiconductor layer whose energy gap is larger than an energy gap of the second oxide semiconductor layer to cover a top surface and side surfaces of the second oxide semiconductor layer;

forming a first mixed region whose composition is different from a composition of the first oxide semiconductor layer and a composition of the second oxide semiconductor layer interposed between the first oxide semiconductor layer and the second oxide semiconductor layer and a second mixed region whose composition is different from a composition of the second oxide semiconductor layer and a composition of the third oxide semiconductor layer interposed between the second oxide semiconductor layer and the third oxide semiconductor layer by performing heat treatment on the oxide semiconductor stack layer;

forming a source electrode layer and a drain electrode layer over the third oxide semiconductor layer;

forming a gate insulating film covering the source electrode layer and the drain electrode layer; and

forming a gate electrode layer over the gate insulating film.

23. The method for manufacturing a semiconductor device according to claim 22, wherein hydrogen or moisture contained in the oxide semiconductor stack layer is released by the heat treatment.

24. The method for manufacturing a semiconductor device according to claim 22, wherein a dopant is added to the oxide semiconductor stack layer in a self-aligned manner using the gate electrode layer as a mask.

25. The method for manufacturing a semiconductor device according to claim 22, wherein the oxide insulating film is formed over a semiconductor substrate including a transistor.

26. The semiconductor device according to claim 22,

wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.