Re-growing Source/Drain Regions from Un-Relaxed Silicon Layer

• US 20130020612A1
• Filed: 07/22/2011
• Published: 01/24/2013
• Est. Priority Date: 07/22/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wann, Clement Hsingjen, Ko, Chih-Hsin, Huang, Yao-Tsung, Huang, Cheng-Ying
• Granted Patent: US 8,609,518 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET.

Claims

1. A method comprising:

forming a silicon germanium layer;

forming a silicon-containing layer over the silicon germanium layer, wherein an atomic percentage of the silicon-containing layer is lower than an atomic percentage of the silicon germanium layer;

forming a gate stack over the silicon-containing layer;

recessing the silicon-containing layer to form a recess adjacent the gate stack; and

epitaxially growing a silicon-containing semiconductor region in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET).

2. The method of claim 1, wherein the silicon germanium layer is relaxed, and the silicon-containing layer is fully un-relaxed, wherein a lattice constant of the silicon-containing layer is greater than 5.43 Å

, and is substantially equal to a lattice constant of the silicon germanium layer.

3. The method of claim 1, wherein the silicon germanium layer is relaxed, and the silicon-containing layer is partially un-relaxed, wherein a lattice constant of the silicon-containing layer is greater than 5.43 Å

, and is substantially smaller than a lattice constant of the silicon germanium layer.

4. The method of claim 1, wherein the silicon germanium layer is fully relaxed.

5. The method of claim 1, wherein the step of epitaxially growing the silicon-containing semiconductor region comprises epitaxially growing a silicon germanium stressor, and wherein the silicon germanium stressor has a germanium atomic percentage lower than a germanium atomic percentage of the silicon germanium layer.

6. The method of claim 1, wherein the step of epitaxially growing the silicon-containing semiconductor region comprises epitaxially growing a silicon stressor, and wherein the silicon stressor is substantially free from germanium.

7. The method of claim 1 further comprising in-situ doping an n-type impurity simultaneously with the step of epitaxially growing the silicon-containing semiconductor region.

8. The method of claim 1, wherein the atomic percentage of the silicon-containing layer is equal to zero.

9. A method comprising:

epitaxially growing a silicon germanium layer over a portion of a silicon substrate;

epitaxially growing a silicon layer over the silicon germanium layer, wherein the silicon germanium layer is relaxed, and the silicon layer is un-relaxed;

forming a gate stack over the silicon layer, wherein a portion of the silicon layer forms a channel region of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET);

recessing the silicon layer to form recesses on opposite sides of the gate stack; and

epitaxially growing silicon germanium stressors in the recesses, wherein the silicon germanium stressors have a germanium atomic percent lower than a germanium atomic percent of the silicon germanium layer, and wherein the silicon germanium stressors form source and drain regions of the NMOS FET.

10. The method of claim 9 further comprising in-situ doping an n-type impurity in the silicon germanium stressors, wherein the step of in-situ doping is performed simultaneously with the step of epitaxially growing the silicon germanium stressors.

11. The method of claim 9, wherein during the step of recessing, top portions of the silicon germanium layer is recessed along with portions of the silicon layer.

12. The method of claim 9, wherein the silicon germanium stressors do not extend into the silicon germanium layer.

13. The method of claim 9, wherein the silicon germanium stressors extends into the silicon germanium layer.

14. A device comprising:

a silicon germanium layer over a silicon substrate, wherein the silicon germanium layer is relaxed;

a silicon layer over the silicon germanium layer, wherein the silicon layer is un-relaxed, and wherein the silicon layer is substantially free from germanium;

a gate stack of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) over the silicon layer, wherein a portion of the silicon layer forms a channel region of the NMOS FET; and

silicon-containing stressors formed in recesses in the silicon layer, wherein the silicon-containing stressors have a lattice constant smaller than a lattice constant of the silicon germanium layer.

15. The device of claim 14, wherein the silicon-containing stressors are substantially free from germanium.

16. The device of claim 14, wherein the silicon-containing stressors comprises germanium, and has a germanium atomic percent lower than a germanium atomic percent of the silicon germanium layer.

17. The device of claim 14, wherein the silicon layer has a thickness smaller than a thickness of the silicon germanium layer.

18. The device of claim 14, wherein the NMOS FET is a FinFET, wherein the silicon layer forms a fin of the FinFET, and wherein the silicon-containing stressors do not extend into the silicon germanium layer.

19. The device of claim 14, wherein the NMOS FET is a FinFET, wherein the silicon layer forms a fin of the FinFET, and wherein the silicon-containing stressors extend into the silicon germanium layer.

20. The device of claim 14, wherein the NMOS FET is a planar NMOS FET.