GATE DIELECTRIC OF SEMICONDUCTOR DEVICE

• US 20130020630A1
• Filed: 07/21/2011
• Published: 01/24/2013
• Est. Priority Date: 07/21/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Da-Yuan, Hsu, Kuang-Yuan
• Granted Patent: US 8,633,536 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having a first, second and third device region;

forming a first dielectric layer in the first region;

thereafter, forming a second dielectric layer in the second region;

forming a hard mask layer on the first device region on the first dielectric layer; and

forming a high-k dielectric layer on the first, second and third device regions, wherein the high-k dielectric layer is formed on the hard mask layer and the second dielectric layer.

2. The method of claim 1, further comprising:

forming the second dielectric layer in the third device region while forming the second dielectric layer in the second device region.

3. The method of claim 2, further comprising:

subsequently, removing the second dielectric layer in the third device region; and

forming a third dielectric layer in the third device region, wherein the high-k dielectric layer is formed on the third dielectric layer.

4. The method of claim 2, wherein the high-k dielectric layer is formed on the second dielectric layer in the third device region.

5. The method of claim 1, further comprising:

forming the hard mask layer on the second device region concurrently with the forming the hard mask layer on the first device region, wherein the hard mask layer is formed on the second dielectric layer.

6. The method of claim 1, wherein the first dielectric layer has a greater thickness than the second dielectric layer.

7. The method of claim 1, wherein the hard mask layer is silicon nitride.

8. The method of claim 1, wherein the high-k dielectric layer formed in the first region provides a gate dielectric for an input/output (I/O) device.

9. A method of fabricating a semiconductor device, the method comprising:

forming a first oxide layer on a first device region of a semiconductor substrate;

forming a second oxide layer on a second device region of the semiconductor substrate, wherein the second oxide layer differs in thickness from the first oxide layer;

forming a hard mask layer on the first oxide layer and the second oxide layer;

forming a dummy gate electrode on the hard mask layer in each of the first and second device regions;

forming a source or drain adjacent the dummy gate electrode in the first device region and a source or drain adjacent the dummy gate electrode in the second device region;

thereafter, removing each of the dummy gate electrodes, wherein the first oxide layer and the second oxide layer remain disposed on the semiconductor substrate during the removal;

forming an interfacial layer in a third device region of the semiconductor substrate;

after removing the dummy gate electrodes, forming a high-k gate dielectric layer on each of the first, second and third device regions, wherein the high-k gate dielectric layer is formed directly on the hard mask layer in the first and second device regions and directly on the interfacial layer in the third device region; and

forming a metal gate electrode on the high-k gate dielectric layer.

10. The method of claim 9, wherein the forming the first oxide layer includes growing the first oxide layer on the first and the second regions of the semiconductor substrate, and subsequently removing the first oxide layer from the second region.

11. The method of claim 9, wherein the first oxide layer is silicon dioxide.

12. The method of claim 9, wherein the forming the interfacial layer includes removing the second dielectric layer.

13. The method of claim 9, wherein the forming the interfacial layer is performed concurrently with the forming the second oxide layer in the second device region, the second oxide layer providing the interfacial layer.

14. The method of claim 9, wherein the forming the hard mask layer includes forming the hard mask layer on the third device region concurrently with the first and second device region, and subsequently removing the hard mask layer from the third device region.

15. The method of claim 9, wherein the forming the hard mask layer includes performing at least one of chemical vapor deposition (CVD) and atomic layer deposition (ALD).

16. The method of claim 9, wherein the forming the hard mask layer includes depositing a nitride based material.

17. A semiconductor device, comprising:

a semiconductor substrate;

a first gate structure formed on the semiconductor substrate, wherein the first gate structure includes a first oxide layer, a nitride layer on the oxide layer, and a high-k dielectric layer on the nitride layer;

a second gate structure formed on the semiconductor device, wherein the second gate structure includes a second oxide layer, the nitride layer on the oxide layer, and the high-k dielectric layer disposed on the nitride layer; and

a third gate structure formed on the semiconductor substrate, wherein the third gate structure includes an interfacial layer and the high-k dielectric layer disposed on the interfacial layer.

18. The semiconductor device of claim 17, further comprising:

a work function layer formed on the high-k dielectric layer of each of the first, second and third gate structures.

19. The semiconductor device of claim 17, wherein the first gate structure is associated with an I/O device.

20. The semiconductor device of claim 17, wherein the second gate structure is associated with a low-power device.