PROCESS FOR PREPARING A BONDING TYPE SEMICONDUCTOR SUBSTRATE

• US 20130020681A1
• Filed: 08/27/2012
• Published: 01/24/2013
• Est. Priority Date: 06/09/1999
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Akaike, Yasuhiko, Yoshitake, Shunji, FURUKAWA, Kazuyoshi
• Granted Patent: US 8,829,488 B2
• Time in Patent Office: Days
• US Class Current: 257/615
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/10 with a light reflecting structure, e.g. semiconductor Bragg reflector
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate

Abstract

Provided is a laminate comprising a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×10″ cm or more.

Claims

1-6. -6. (canceled)

7. A laminate comprising:

a first compound semiconductor layer; and

a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer,

wherein a surface where a plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer, and

wherein an impurity concentration of the bonding layer being 2×

10″

cm or more.

8. The laminate according to claim 7, wherein the bonding layer icomprises an epitaxial growth layer.

9. The laminate according to claim 8, wherein the epitaxial growth layer comprises a InGaAlP layer or a GaP layer.

10. The laminate according to claim 7, wherein the bonding layer comprises a bonding material.