INTEGRATED CIRCUIT SYSTEMS INCLUDING VERTICAL INDUCTORS

• US 20130027127A1
• Filed: 07/29/2011
• Published: 01/31/2013
• Est. Priority Date: 07/29/2011
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Topaloglu, Rasit O.
• Granted Patent: US 9,159,711 B2
• Time in Patent Office: Days
• US Class Current: 327/564
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit system is provided that includes a circuit function in and on a surface of a semiconductor substrate. First and second portions of an inductor overlie the surface of the semiconductor substrate and each is coupled to the first circuit function. A third portion of the inductor is positioned on a second substrate. A first through substrate via (TSV) extends through the semiconductor substrate and electrically couples the first portion to the third portion and a second TSV extends through the semiconductor substrate and electrically couples the second portion to the third portion.

Claims

1. An integrated circuit system comprising:

a first circuit function in and on a surface of a semiconductor substrate;

a first portion and a second portion of an inductor overlying the surface of the semiconductor substrate, the first portion coupled to the circuit function;

a third portion of the inductor overlying a second substrate;

a first through substrate via extending through the semiconductor substrate and electrically coupled to the first portion and the third portion; and

a second through substrate via extending through the semiconductor substrate and electrically coupled to the second portion and the third portion.

3. The integrated circuit system of claim 1 wherein the second substrate comprises a second semiconductor substrate and wherein the second semiconductor substrate includes a second circuit function.

4. The integrated circuit system of claim 1 further comprising:

a third through substrate via electrically coupled to the first portion and the third portion; and

a fourth through substrate via electrically coupled to the second portion and the third portion.

5. The integrated circuit system of claim 1 wherein the second substrate comprises an interposer substrate having a plurality of semiconductor die mounted thereon.

6. The integrated circuit system of claim 1 wherein the first through substrate via and the second through substrate via extend through the semiconductor substrate from the surface to a back surface, the integrated circuit system further comprising a redistribution layer positioned overlying the back surface.

7. The integrated circuit system of claim 1 further comprising a second inductor comprising:

a fourth portion on the surface of the semiconductor substrate and coupled to the circuit function;

a fifth portion positioned on the second substrate; and

a plurality of through substrate vias coupling the fourth portion to the fifth portion to form an inductor loop.

8. The integrated circuit system of claim 1 wherein each of the first portion, second portion, third portion, first through substrate via and second through substrate via comprise copper.

9. The integrated circuit system of claim 1 further comprising:

a fourth portion of the inductor overlying the second substrate and a fifth portion of the inductor overlying the semiconductor substrate, the fifth portion coupled to the circuit function;

a third through substrate via extending through the semiconductor substrate and electrically coupled to the second portion and the fourth portion; and

a fourth through substrate via extending through the semiconductor substrate and electrically coupled to the fourth portion and the fifth portion.

2. The integrated circuit system of claim 2 further comprising a plurality of through substrate vias spaced apart from and positioned between the first circuit function and the first portion and the second portion and configured to be coupled to ground.

10. An integrated circuit system comprising:

a circuit function in and on a surface of a semiconductor substrate;

a first portion and a second portion of an inductor overlying the surface and coupled to the circuit function;

N additional inductor portions where N is greater than 1, each of the N additional inductor portions positioned on one of N additional substrates; and

a plurality of through substrates vias coupling the N+2 portions to form a completed inductor loop.

11. The integrated circuit system of claim 10 wherein the plurality of through substrate vias comprise a variety of different cross sectional areas.

12. The integrated circuit system of claim 10 wherein spacing between adjacent ones of the semiconductor substrate and the N additional substrates is nonuniform.

13. The integrated circuit system of claim 10 wherein at least one of the N additional substrates is a semiconductor substrate including a second circuit function.

14. The integrated circuit system of claim 10 wherein at least an (m−

1)^th one of the N additional inductor portions is coupled to an (m+1)^th one of the additional inductor portions by a through substrate via passing through an m^th one of the N additional substrates.

15. The integrated circuit system of claim 10 wherein at least one pair of adjacent ones of the semiconductor substrate and N additional substrates is in front to front relationship and wherein at least one other pair of adjacent ones of the semiconductor substrate and N additional substrates is in front to back side relationship.

16. An integrated circuit system comprising:

a circuit function fabricated in and on a surface of a semiconductor substrate;

a first inductor coupled to the circuit function and positioned in a plane parallel to the surface;

a second inductor coupled to the circuit function comprising;

a first portion overlying the surface;

a second portion positioned overlying a second surface parallel to the surface of the semiconductor substrate and coupled to the first portion by through substrate vias.

17. The integrated circuit system of claim 16 wherein the circuit function comprises:

a sensor portion; and

a communication portion coupled to receive data from the sensor portion.

18. The integrated circuit system of claim 17 wherein the communication portion is configured to transmit signals responsive to the data.

19. The integrated circuit system of claim 16 wherein the second portion is positioned overlying a second surface of the semiconductor substrate.

20. The integrated circuit system of claim 16 wherein the second portion is positioned overlying a second surface of a second substrate physically connected to the semiconductor substrate.