BACK-TO-BACK STACKED DIES

• US 20130043940A1
• Filed: 01/26/2012
• Published: 02/21/2013
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Hebert, Francois, Rivet, Steven R., Althar, Michael, Oaklander, Peter
• Granted Patent: US 9,524,957 B2
• Time in Patent Office: Days
• US Class Current: 327/564
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32013 the layer connector being larger than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83855 : Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3732 : Diamonds
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49517 : Additional leads
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1425 : Converter
• CPC Class Codes: H01L 2924/14253 : Digital-to-analog converter [DAC]
• CPC Class Codes: H01L 2924/1426 : Driver
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device

Abstract

Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

Claims

1. A circuit comprising:

a first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier; and

a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

2. The circuit of claim 1, wherein the first die includes a metal layer on the backside.

3. The circuit of claim 2, comprising one or more bond wires coupling the metal layer of the first die to the carrier.

4. The circuit of claim 3, wherein the metal layer is coupled to one of a DC ground, a DC bias voltage, or a filter network.

5. The circuit of claim 1, wherein the backside of the second die is electrically coupled to the backside of the first die.

6. The circuit of claim 5, wherein the second die is mounted to the first die using one of an electrically conductive epoxy or solder.

7. The circuit of claim 1, wherein the first die has a lateral structure and includes a high side device and a low side device;

and

wherein the second die has a lateral structure and includes a controller for the high side device and the low side device.

8. The circuit of claim 1, comprising:

a chip package surrounding the first die and the second die, wherein the carrier includes a plurality of pins, wherein the first die is mounted such that the active side is coupled to one or more of the plurality of pins.

9. The circuit of claim 8, comprising bond wires coupling the active side of the second die to a subset of the plurality of pins, wherein the subset of the plurality of pins are disposed at least partially outward from a footprint of the first die.

10. The circuit of claim 9, wherein a subset of the plurality of pins are disposed to be partially opposite the active side of the first die and partially outward from a footprint of the first die, wherein the subset is coupled to the active side of the first die and to one or more of the plurality of bond wires.

11. The circuit of claim 8, comprising a thermal plug thermally coupled to the backside of the first die and exposed at an outer surface of the chip package.

12. The circuit of claim 1, wherein first die includes diamond on the backside.

13. The circuit of claim 1, wherein the second die is mounted to the first die using a non-electrically conductive epoxy.

14. The circuit of claim 1, wherein the first die includes a substrate selected from the group comprising:

silicon, silicon on insulator, silicon on diamond, silicon on diamond on silicon, gallium nitride, gallium arsenide.

15. The circuit of claim 1, wherein the first die includes one of a P−

substrate, Pepi on P−

substrate, Pepi on P+ substrate.

16. The circuit of claim 1, wherein the first die includes one of solder bumps, copper pillars, or solderable pads on the active side.

17. The circuit of claim 1, wherein the circuit comprises a power conversion system including one of a DC-to-DC power converter, a charger, a hot-swap controller, a AC-DC converter, a bridge driver, a buck converter, a boost converter, a buck-boost converter, and a synchronous buck converter.

18. The circuit of claim 1, comprising:

a third die stacked on the backside of the first die, wherein the third die is stacked on the first die such that a backside of the third die is facing the backside of the first die and an active side of the third die faces away from the first die.

19. The circuit of claim 18, wherein the first die includes a high side device and a low side device, wherein the high side and low side devices have a lateral structure;

wherein the second die includes a controller for the high side device and the low side device; and

wherein the third die includes a driver for the high side device and the low side device.

20. An integrated circuit (IC) comprising:

a lead frame structure;

a first die with an active side and a backside, the first die mounted to the lead frame structure such that the active side faces the lead frame structure and is coupled to the lead frame structure;

a second die with an active side and a backside, the second die stacked on the first die such that the backside of the second die is facing the backside of the first die; and

a plurality of bond wires coupled to the active side of the second die and to the lead frame structure.

21. The IC of claim 20, wherein the first die includes a metal layer on the backside, the packaged IC including one or more bond wires coupling the metal layer of the first die to the lead frame structure.

22. The IC of claim 20, comprising:

one of an electrically conductive epoxy or solder physically connecting and electrically coupling the backside of the second die to the backside of the first die.

23. The IC of claim 20, wherein the first die includes a power stage having a high side device and a low side device;

and

wherein the second die includes a controller for the high side device and the low side device.

24. The IC of claim 23, comprising:

a third die stacked on the backside of the first die, wherein the third die is stacked on the first die such that a backside of the third die is facing the backside of the first die and an active side of the third die faces away from the first die, wherein the third die includes a driver for the high side device and the low side device.

25. The IC of claim 20, comprising:

a molding compound around the first die and the second die; and

a thermal plug thermally coupled to the backside of the first die and exposed at an outer surface of the molding compound.

26. The IC of claim 20, wherein first die includes diamond on the backside.

27. The IC of claim 20, wherein the first die includes one of solder bumps, copper pillars, or solderable pads coupling the active side to the lead frame structure.

28. A power conversion system comprising:

a power stage monolithic integrated circuit (IC) having a lateral structure including an active side and a backside, the active side of the power stage monolithic IC mounted to a carrier;

a controller monolithic IC having a lateral structure including an active side and a backside, the controller monolithic IC stacked on the power stage monolithic IC, the backside of the controller monolithic IC mounted to the backside of the power stage monolithic IC, wherein the controller monolithic IC is configured to control the power stage IC; and

a plurality of bond wires coupled to the active side of the controller monolithic IC and the carrier.

29. The power conversion system of claim 28, wherein the power stage monolithic IC includes a high side field effect transistor (FET) and a low side FET configured to implement a synchronous buck converter.

30. The power conversion system of claim 28, wherein the power stage monolithic IC includes a high side field effect transistor (FET) and a low side diode configured to implement a non-synchronous buck converter.

31. The power conversion system of claim 28, wherein the power stage monolithic IC includes a low side field effect transistor (FET) and a Schottky diode coupled in series with an output load.

32. The power conversion system of claim 28, comprising:

a driver monolithic IC having a lateral structure with an active side and a backside, the driver monolithic IC stacked on the backside of the power stage monolithic IC, the backside of the driver monolithic IC mounted to the backside of the power stage monolithic IC, the drive monolithic IC configured to drive the power stage monolithic IC.

33. The power conversion system of claim 28, comprising:

a chip package around the power stage monolithic IC, the controller monolithic IC, and the plurality of bond wires.

34. The power conversion system of claim 28, wherein the carrier includes a printed circuit board.

35. A method of manufacturing a packaged circuit having a first die mounted on an inverted second die, the method comprising:

mounting the second die to a lead frame such that an active side of the second die is attached to the lead frame;

mounting the first die to the backside of the second die such that a backside of the first die is attached to the backside of the second die; and

electrically coupling the active side of the first die to the lead frame.

36. The method of claim 35, wherein the first die and the second die have a lateral structure, and wherein the first die comprises a controller and the second die comprises a power stage.

37. The method of claim 35, wherein mounting the second die to a lead frame includes electrically coupling the second die to the lead frame using one or more of solder balls on the second die or solder on pads of the lead frame.

38. The method of claim 35, wherein mounting the first die to the backside of the second die includes using one of solder or epoxy to attach the backside of the first die to the backside of the second die.

39. The method of claim 35, wherein electrically coupling the active side of the first die to the lead frame includes wire bonding, using one or more copper clips, or using one or more aluminum ribbons.

40. The method of claim 35, comprising:

electrically coupling the backside of the second die to the lead frame.

41. The method of claim 35, comprising:

attaching a thermal plug to the backside of the second die; and

grinding the molding compound to expose the thermal plug.

42. The method of claim 35, comprising:

mounting a third die to the backside of the second die such that a backside of the third die is attached to the backside of the second die; and

electrically coupling an active side of the third die to the active side of the first die.

43. The method of claim 35, comprising:

depositing molding compound over the second die and the first die; and

curing the molding compound.

44. An electronic device comprising:

one or more processing devices;

one or more memory devices communicatively coupled to the one or more processing devices; and

one or more power conversion systems coupled to the one or more processing devices and the one or more memory devices, the one or more power conversion systems having a controller die mounted on a power stage die such that a backside of the controller die is attached to a backside of the power stage die and configured to provide regulated power to the one or more processing devices and the one or more memory devices.

45. The electronic device of claim 44, wherein the electronic device comprises one of desktop, laptop, or tablet computer, a set top box, or a battery charger.