METHOD AND STRUCTURE FOR ADVANCED SEMICONDUCTOR CHANNEL SUBSTRATE MATERIALS

• US 20130052813A1
• Filed: 08/30/2011
• Published: 02/28/2013
• Est. Priority Date: 08/30/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YEH, Ming-Hsi, LIN, Chin-Hsiang, LEE, Chun-Yi, YANG, Chi-Ming
• Granted Patent: US 9,165,835 B2
• Time in Patent Office: Days
• US Class Current: 438/527
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

Provided is a method and structure for utilizing advance channel substrate materials in semiconductor manufacturing. Advanced channel substrate materials such as germanium and Group III-V channel substrate materials, are advantageously utilized. One or more capping films including at least a nitride layer are formed over the channel substrate prior to patterning, ion implantation and the subsequent stripping and wet cleaning operations. With the capping layers intact during these operations, attack of the channel substrate material is prevented and the protective films are easily removed subsequently. The films are dimensioned in conjunction with the ion implantation operation to enable the desired dopant profile and concentration to be formed in the channel substrate material.

Claims

1. A method for forming a semiconductor device, said method comprising:

providing a channel substrate of a substrate material being one of Ge, SiGe, GaAs, InP, InGaAs and a further Group III-V semiconductor material;

forming a film structure comprising a nitride layer over said channel substrate;

performing at least one ion implantation processing sequence;

removing said film structure; and

performing further processing operations.

2. The method as in claim 1, wherein said at least one ion implantation processing sequence comprises a plurality of said ion implantation processing sequences and wherein each said ion implantation processing sequence includes forming a photoresist pattern, removing said photoresist pattern and cleaning said channel substrate after said removing.

3. The method as in claim 2, wherein said cleaning said channel substrate comprises wet cleaning using at least one of HCl, HF, HNO₃, H₂SO₄, APM, HPM and Caros acid.

4. The method as in claim 2, wherein said substrate material comprises SiGe and said plurality of ion implantation processing sequences include at least one p-well ion implantation processing operation and at least one n-well ion implantation processing operation.

5. The method as in claim 1, wherein said performing at least one ion implantation processing sequence comprises a plurality of ion implantation processing sequences including a plurality of wet chemical cleaning operations, each said wet chemical cleaning operation utilizing at least one of HCl, HF, HNO₃, H₂SO₄, APM, HPM and Caros acid.

6. The method as in claim 1, wherein said providing a channel substrate comprises forming said channel substrate over a silicon wafer.

7. The method as in claim 6, wherein said channel substrate includes a thickness of about 1000-2500 angstroms.

8. The method as in claim 1, wherein said channel substrate comprises an upper channel region of a substrate formed of said substrate material.

9. The method as in claim 1, wherein said providing a channel substrate includes forming shallow trench isolation (STI) structures within said channel substrate.

10. The method as in claim 1, wherein said nitride layer comprises a silicon oxynitride layer.

11. The method as in claim 1, wherein said forming a film structure comprising a nitride layer comprises forming an oxide layer on said channel substrate and forming a silicon nitride layer over said oxide layer.

12. The method as in claim 11, wherein said oxide layer includes a thickness of about 5-15 angstroms and said silicon nitride layer includes a thickness of about 10-50 angstroms.

13. The method as in claim 11, wherein said forming an oxide layer comprises forming a chemical oxide layer using ozone and deionized water.

14. The method as in claim 1, wherein said channel substrate comprises a planar substrate.

15. The method as in claim 1, wherein said providing a channel substrate includes fin structures forming part of said channel substrate.

16. The method as in claim 1, wherein said further processing includes forming polysilicon gate structures over said channel substrate, forming a further film structure comprising at least a nitride layer over said channel substrate including over said polysilicon gate structures, forming a photoresist pattern and performing a source/drain ion implantation, removing said photoresist pattern, performing a wet chemical cleaning operation using at least one of HCl, HF, HNO₃, H₂SO₄, APM, HPM and Caros acid, and removing said further film structure.

17. A method for forming a semiconductor device, said method comprising:

providing a channel substrate of a substrate material being one of Ge, SiGe, GaAs, InP, InGaAs and a further Group III-V semiconductor material;

forming a film structure comprising a nitride layer over said channel substrate;

performing a plurality of ion implantation processing sequences;

removing said film structure;

forming polysilicon gate structures over said channel substrate;

forming a further film structure comprising a further nitride layer over said channel substrate including over said polysilicon gate structures;

forming a photoresist pattern and performing a source/drain ion implantation;

removing said photoresist pattern;

performing a wet chemical cleaning operation using at least one of HCl, HF, HNO₃, H₂SO₄, APM, HPM and Caros acid; and

removing said further film structure.

18. The method as in claim 17, wherein said providing a channel substrate includes fin structures forming part of said channel substrate.

19. The method as in claim 17, wherein each said ion implantation processing sequence includes forming a photoresist pattern, performing a well ion implantation processing operation, removing said photoresist pattern and cleaning said channel substrate using at least one of HCl, HF, HNO₃, H₂SO₄, APM, HPM and Caros acid, after said removing.

20. The method as in claim 17, wherein said forming a film structure comprises forming an oxide layer on said channel substrate and forming a silicon nitride layer over said oxide layer and said forming a further film structure comprises said further nitride layer being a silicon oxynitride layer.