High Voltage Device and Manufacturing Method Thereof

• US 20130069153A1
• Filed: 09/17/2011
• Published: 03/21/2013
• Est. Priority Date: 09/17/2011
• Status: Active Grant

• Current Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Original Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Inventors: Huang, Tsung-Yi, Huang, Chien-Hao
• Granted Patent: US 8,963,237 B2
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.

Claims

1. A high voltage device comprising:

a substrate, having an isolation structure for defining a device region;

a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another;

a source and a drain in the device region; and

a gate on the surface of the substrate and between the source and drain in the device region.

2. The high voltage device of claim 1, further comprising a well region surrounding the source and having a different conductive type from that of the source.

3. The high voltage device of claim 2, wherein the well region and the drift region are located at different horizontal positions and are separated from one the other.

4. The high voltage device of claim 1, further comprising buffer regions located at two different sides of the drain.

5. The high voltage device of claim 4, wherein the multiple sub-regions are electrically connected with one another via the buffer regions.

6. The high voltage device of claim 1, wherein the multiple sub-regions are electrically connected with one another via a connection region or at least one wire.

7. The high voltage device of claim 1, wherein a low voltage device having a lightly doped drain (LDD) is formed on the substrate, and wherein the LDD and the drift region are formed at least partially by a same process step.

8. A method for manufacturing high voltage device comprising:

providing a substrate, and forming an isolation structure in the substrate to define a device region;

forming a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another;

forming a source and a drain in the device region; and

forming a gate on the surface of the substrate and between the source and drain in the device region.

9. The method of claim 8, further comprising forming a well region surrounding the source and having a different conductive type from that of the source.

10. The method of claim 9, wherein the well region and the drift region are located at different horizontal positions and are separated from one the other.

11. The method of claim 8, further comprising buffer regions located at two different sides of the drain.

12. The method of claim 11, wherein the multiple sub-regions are electrically connected with one another via the buffer region.

13. The method of claim 8, wherein the multiple sub-regions are electrically connected with one another via a connection region or at least one wire.

14. The method of claim 8, wherein a low voltage device having a lightly doped drain (LDD) is formed on the substrate, and wherein the LDD and the drift region are formed at least partially by a same process step.