DAMASCENE PROCESS FOR ALIGNING AND BONDING THROUGH-SILICON-VIA BASED 3D INTEGRATED CIRCUIT STACKS

• US 20130069232A1
• Filed: 09/16/2011
• Published: 03/21/2013
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Yu, Hong, Liu, Huang
• Granted Patent: US 8,877,637 B2
• Time in Patent Office: Days
• US Class Current: 257/741
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

Through-silicon-via (TSV) based 3D integrated circuit (3D IC) stacks are aligned, bonded and electrically interconnected using a transparent alignment material in the TSVs until the wafers are bonded. Embodiments include providing a first wafer having a first device layer and at least one first TSV filled with a conductive material, providing a second wafer having a second device layer, forming at least one second TSV in the second wafer, filling each second TSV with an alignment material, thinning the second wafer until the transparent material extends all the way through the wafer, aligning the first and second wafers, bonding the first and second wafers, removing the alignment material from the second wafer, and filling each second TSV in the second wafer with a conductive material.

Claims

1. A method comprising:

providing a first wafer having first and second surfaces, a first device layer, and at least one through-silicon-via (TSV) filled with a conductive material;

providing a second wafer having first and second surfaces and a second device layer on the first surface;

forming at least one second TSV in the first surface of the second wafer;

filling each second TSV in the second wafer with an alignment material;

thinning the second surface of the second wafer;

aligning the first and second wafers;

bonding the first and second wafers;

removing the alignment material from the second wafer; and

filling each second TSV in the second wafer with a conductive material.

2. The method according to claim 1, comprising forming the at least one second TSV in the first surface of the second wafer by etching.

3. The method according to claim 1, comprising filling each second TSV in the second wafer with an alignment material transparent to at least one of infrared, visible, and ultraviolet (UV) light.

4. The method according to claim 3, comprising filling by:

forming a layer of the alignment material; and

chemical mechanical polishing (CMP) down to the first surface of the second wafer.

5. The method according to claim 3, comprising filling by:

forming a layer of the alignment material; and

etching down to the first surface of the second wafer.

6. The method according to claim 1, comprising thinning the second surface of the second wafer until the alignment material extends all the way through the wafer.

7. The method according to claim 1, comprising bonding the first and second wafers by forming an adhesive bonding layer on at least one surface of the first or second wafer.

8. The method according to claim 7, comprising aligning each first TSV in the first wafer with a corresponding second TSV filled with the transparent alignment material in the second wafer.

9. The method according to claim 8, comprising removing the alignment material in the second wafer and the adhesive bonding layer by etching to expose each first TSV filled with conductive material in the first wafer.

10. The method according to claim 9, comprising cleaning with dilute hydrofluoric acid (dHF) each exposed TSV filled with conductive material in the first wafer subsequent to removing the alignment material and adhesive bonding layer.

11. The method according to claim 1, comprising filling each second TSV in the second wafer with copper.

12. The method according to claim 1, comprising forming by electrochemical plating (ECP) a layer of conductive material on an outer surface of and in each second TSV of the second wafer.

13. The method according to claim 12, comprising chemical mechanical polishing (CMP) down to the outer surface of the second wafer.

14. A method comprising:

providing a first wafer having first and second surfaces, a first device layer, and at least one through-silicon-via (TSV) filled with a conductive material;

providing a second wafer having first and second surfaces, a second device layer, and at least one second TSV corresponding to the at least one first TSV of the first wafer;

aligning each first TSV in the first wafer with the corresponding second TSV in the second wafer;

bonding the first and second wafers; and

electrically interconnecting the first and second wafers through the first and second TSVs.

15. The method according to claim 14, comprising providing a first wafer having at least two first TSVs filled with a conductive material and a second wafer having at least two second TSVs.

16. The method according to claim 14, wherein the at least two second TSVs are filled with an alignment material transparent to at least one of infrared, visible, and ultraviolet (UV) light, and the method further comprising removing the transparent alignment material subsequent to bonding.

17. The method according to claim 14, comprising forming an adhesive bonding layer on at least one surface of the first or second wafer.

18. The method according to claim 14, comprising forming by electrochemical plating (ECP) a layer of conductive material on an outer surface and in each second TSV in the second wafer and further comprising removing by chemical mechanical polishing (CMP) any excess conductive material from the outer surface of the second wafer.

19. A method comprising:

providing a first wafer having first and second surfaces, a first device layer, and at least two through-silicon-vias (TSVs) filled with copper;

providing at least two second wafers, each having first and second surfaces and a second device layer on the first surface;

etching at least two second TSVs in the first surface of each second wafer;

filling each second TSV in each second wafer with an alignment material which is transparent to at least one of infrared, visible, and ultraviolet (UV) light;

thinning the second surface of each second wafer until the alignment material extends all the way through the wafer;

aligning the first TSVs in the first wafer with the second TSVs in one second wafer;

bonding the first wafer and the one second wafer with an adhesive bonding material;

etching the alignment and bonding materials through the second TSVs of the one second wafer, to expose the filled first TSVs of the first wafer;

filling the second TSVs in the one second wafer with copper; and

repeating for each additional second wafer the steps comprising;

aligning the second TSVs in the bonded second wafer with the second TSVs in an additional second wafer;

bonding further the bonded second wafer with the additional second wafer;

etching the alignment and bonding material in the second TSVs of the additional second wafer thereby exposing the filled second TSVs of the bonded second wafer; and

filling the second TSVs of the additional second wafer with copper.

20. A TSV based 3D integrated circuit (IC) stack produced by the method according to claim 19.