METHOD FOR FABRICATING A FINFET DEVICE

• US 20130071980A1
• Filed: 11/09/2012
• Published: 03/21/2013
• Est. Priority Date: 02/11/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Hsien-Hsin, Kwok, Tsz-Mei, Su, Chien-Chang
• Granted Patent: US 8,652,894 B2
• Time in Patent Office: Days
• US Class Current: 438/300
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes forming a fin structure on a semiconductor substrate and forming a gate structure on the fin structure. A capping layer is then formed over the semiconductor substrate, fin structure, and gate structure. The capping layer is patterned to form an opening exposing a second portion of the fin structure. An epitaxial layer is grown in the opening and on the second portion of the fin structure. At least one of a source region and a drain region is provided in the epitaxial layer. The method may continue to remove the capping layer.

Claims

1. A method for fabricating a FinFET device comprising:

forming a fin structure on a semiconductor substrate;

forming a gate structure, wherein the gate structure overlies a first portion of the fin structure;

forming a capping layer over the semiconductor substrate, fin structure, and gate structure;

patterning the capping layer to form an opening, wherein the opening exposes a second portion of the fin structure; and

growing an epitaxial layer in the opening and on the second portion of the fin structure, wherein the epitaxial layer includes at least one of a source region and a drain region associated with the gate structure.

2. The method of claim 1, wherein the forming the capping layer includes depositing an oxide capping layer.

3. The method of claim 1, further comprising:

removing the capping layer after growing the epitaxial layer.

4. The method of claim 1, wherein the patterning the capping layer to form the opening includes removing a portion of the capping layer to define a profile of the source and drain regions.

5. The method of claim 1, wherein the growing the epitaxial layer in the opening comprises forming a source and a drain each having a square profile.

6. The method of claim 1, wherein the patterning the capping layer to form the opening includes performing at least one photolithography process and at least one etch process.

7. The method of claim 1, wherein the growing the epitaxial layer in the opening includes performing a selective epitaxy growth process to form at least one of a silicon layer and a silicon germanium layer.

8. The method of claim 1, further comprising:

prior to forming the capping layer, forming a recessed region in the second portion of the fin structure.

9. The method of claim 1, further comprising:

performing a first chemical mechanical polishing process on the capping layer.

10. The method of claim 9, further comprising:

performing a second chemical mechanical polishing process on the grown epitaxial layer.

11. A method for fabricating a FinFET device comprising:

forming a fin structure on a substrate;

forming a gate structure on first region of the fin structure;

removing a second region of the fin structure to form a recessed portion of the fin structure;

forming a capping layer over the first and second regions of the fin structure;

patterning the capping layer to form an opening that defines a source and drain region associated with the gate structure, wherein the opening exposes the recessed portion of the fin structure;

growing an epitaxial layer on the exposed recessed portion of the fin structure in the opening of the capping layer; and

removing the capping layer after growing the epitaxial layer.

12. The method of claim 11, wherein the providing the substrate including the fin structure includes providing a silicon substrate having a (001) crystallographic orientation.

13. The method of claim 11, wherein the growing the epitaxial layer on the exposed recessed portion of the fin structure comprises forming a source and a drain having a square profile.

14. The method of claim 11, wherein the growing the epitaxial layer on the exposed recessed portion of the fin structure comprises forming a raised source and a raised drain.

15. The method of claim 11, further comprising:

performing an ion implantation process on the epitaxial layer.

16. A method of fabricating a FinFET device comprising:

providing a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation;

forming a fin structure of the crystalline semiconductor material overlying the substrate;

forming a gate structure over a first portion of the fin structure;

growing an epitaxy layer over a second portion of the fin structure adjacent the first portion, wherein a surface of the epitaxy layer substantially perpendicular to the top surface has a second crystal plane orientation, the second crystal plane orientation different than the first crystal plane orientation; and

forming a channel region in the fin structure, wherein the channel region is aligned in a direction parallel to both the first surface of the epitaxy layer and the top surface of the substrate.

17. The method of claim 16, wherein the growing the epitaxy layer includes performing a damascene process that includes:

forming a capping layer over the substrate, the fin structure, and the gate structure;

patterning the capping layer to form an opening, wherein the opening exposes the second portion of the fin structure;

growing the epitaxy layer in the opening on the exposed second portion of the fin structure; and

removing the capping layer.

18. The method of claim 16, wherein the growing the epitaxy layer includes performing a damascene process that includes:

removing a third portion of the fin structure overlying the second portion of the fin structure, to form a recessed portion of the fin structure;

forming a capping layer over the substrate, fin structure, and gate structure;

patterning the capping layer to form an opening, wherein the opening exposes the recessed portion of the fin structure;

growing the epitaxy layer in the opening on the exposed recessed portion of the fin structure; and

removing the capping layer.

19. The method of claim 16, wherein growing the epitaxy layer further includes performing an implantation process.

20. The method of claim 16, wherein a region in which the growing of the epitaxy layer is performed is defined by a sacrificial capping layer.