Trap Rich Layer Formation Techniques for Semiconductor Devices

• US 20130084689A1
• Filed: 11/26/2012
• Published: 04/04/2013
• Est. Priority Date: 12/24/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: IO Semiconductor, Inc
• Inventors: Stuber, Michael A., Molin, Stuart B., Arriagada, Anton
• Granted Patent: US 8,536,021 B2
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: H01L 21/02365 Forming inorganic semiconducting materials on a substrate for light-sensitive devices H01L31/00
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76243 using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00

Abstract

A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

Claims

1. A method comprising:

forming a trap rich layer for an integrated circuit by chemical etching or laser texturing of a surface of a semiconductor layer; and

forming a circuit layer for the integrated circuit.

2. The method of claim 1, wherein:

the trap rich layer is formed by chemical etching; and

the forming of the trap rich layer further comprises damaging the surface of the semiconductor layer before the chemical etching.

3. The method of claim 2, wherein:

the damaging of the surface further comprises laser texturing the surface of the semiconductor layer.

4. The method of claim 2, wherein:

the damaging of the surface further comprises mechanical texturing the surface of the semiconductor layer.

5. The method of claim 1, wherein:

the trap rich layer is formed by chemical etching; and

the chemical etching is non-uniform.

6. The method of claim 1, further comprising:

layer transferring a first structure containing the trap rich layer with a second structure containing the circuit layer.

7. The method of claim 1, wherein:

the forming of the trap rich layer further comprises projecting energetic particles towards the semiconductor layer.

8. The method of claim 1, wherein:

the trap rich layer is formed by chemical etching; and

the chemical etching further comprises wet chemical etching of the surface of the semiconductor layer.

9. The method of claim 1, wherein:

the trap rich layer is formed by chemical etching; and

the chemical etching further comprises dry chemical etching of the surface of the semiconductor layer.

10. The method of claim 1, wherein:

the forming of the trap rich layer is performed on a structure to contain the circuit layer before the forming of the circuit layer.

11. The method of claim 1, wherein:

the forming of the trap rich layer is performed on a structure containing the circuit layer after the forming of the circuit layer.

12. The method of claim 1, wherein:

the trap rich layer remains in a final structure for the integrated circuit.

13. A method comprising:

forming a trap rich layer for an integrated circuit by laser texturing of a surface of a semiconductor layer; and

forming a circuit layer for the integrated circuit.

14. The method of claim 13, wherein:

the forming of the trap rich layer further comprises the laser texturing combined with a chemical etching of the surface of the semiconductor layer.

15. The method of claim 13, wherein:

the forming of the trap rich layer by laser texturing further comprises directing a laser at a non-perpendicular angle to the surface of the semiconductor layer and rotating the semiconductor layer.

16. A method comprising:

in a semiconductor wafer, forming a trap rich layer by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing.

17. The method of claim 16, further comprising:

forming the trap rich layer by at least two of the techniques selected from the group of techniques.

18. The method of claim 16, wherein:

the forming of the trap rich layer further comprises combining at least one technique selected from the first group of techniques with at least one additional technique selected from a second group of techniques consisting of depositing polysilicon on a surface of the semiconductor wafer, depositing amorphous silicon on the surface of the semiconductor wafer, recrystallizing polysilicon at the surface of the semiconductor wafer, and damaging the surface of the semiconductor wafer by ion implantation.

19. The method of claim 16, wherein:

the forming of the trap rich layer is performed on a structure to contain a circuit layer before forming of the circuit layer.

20. The method of claim 16, wherein:

the forming of the trap rich layer is performed on a structure containing a circuit layer after forming of the circuit layer.