Method for Reducing Forming Voltage in Resistive Random Access Memory

• US 20130089949A1
• Filed: 11/09/2012
• Published: 04/11/2013
• Est. Priority Date: 10/06/2011
• Status: Active Grant

• Current Assignee: Intermolecular Incorporated
• Original Assignee: Intermolecular Incorporated
• Inventors: Phatak, Prashant B., Tong, Jinhong, Kuse, Ronald J.
• Granted Patent: US 8,822,265 B2
• Time in Patent Office: Days
• US Class Current: 438/104
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/041 Modification of the switching material, e.g. post-treatment, doping
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways.

Claims

1. A method for producing resistive switching elements, the method comprising:

depositing a first electrode onto a substrate;

depositing a first resistive switching film onto the first electrode,

wherein the first resistive switching film comprises a first dielectric material configured to develop conductive pathways during application of a predetermined voltage and further configured to maintain said conductive pathways after said predetermined voltage is removed,

wherein depositing the first resistive switching film does not cause formation of an interfacial oxide layer on the first electrode; and

depositing a second electrode.

2. The method of claim 1, wherein the first resistive switching film comprises hafnium oxide.

3. The method of claim 1, further comprising depositing a second resistive switching film onto the first resistive switching film prior to depositing the second electrode, wherein the first resistive switching layer and the second resistive switching layer form a stack, the stack being configured to develop conductive pathways during application of a predetermined voltage and further configured to maintain said conductive pathways after said predetermined voltage is removed.

4. The method of claim 3, wherein the second resistive switching film comprises titanium oxide.

5. The method of claim 4, wherein the first resistive switching film comprises hafnium oxide.

6. The method of claim 1, wherein the first electrode comprises polycrystalline silicon.

7. The method of claim 1, wherein the second electrode comprises one of titanium nitride or polycrystalline silicon.

8. The method of claim 1, wherein depositing the first resistive switching film is performed by atomic layer deposition (ALD) at a deposition temperature low enough to prevent oxidation in the first electrode.

9. The method of claim 8, wherein the first resistive switching film is deposited using TDMAH, and wherein the TDMAH is maintained at a temperature between 40°

C. and 50°

C.

10. The method of claim 1, further comprising depositing a second film onto the first resistive switching film prior to depositing the second electrode, wherein the second film comprises as a dopant of the first resistive switching film.

11. The method of claim 10, wherein the first resistive switching film comprises at least one tetravalent metal oxide and wherein the second film comprises at least one trivalent metal oxide.

12. The method of claim 1, further comprising depositing a second resistive switching film onto the first resistive switching film prior to depositing the second electrode, wherein the second resistive switching film comprises a material having a band gap greater than the band gap of a material forming the first resistive switching film.

13. The method of claim 12, further comprising depositing a third resistive switching film onto the second resistive switching film prior to depositing the second electrode, wherein the third resistive switching film comprises a dielectric with a band gap greater than the band gap of a material forming the second resistive switching film.

14. The method of claim 13, further comprising depositing a fourth resistive switching film onto the third resistive switching film prior to depositing the second electrode, wherein the fourth resistive switching film comprises a dielectric with a band gap greater than the band gap of a material forming the third resistive switching film.

15. The method of claim 1, further comprising converting polysilicon of the first electrode into a conducting silicide.

16. The method of claim 1, further comprising depositing a second resistive switching film onto the first resistive switching film prior to depositing the second electrode, the first resistive switching film being deposited using physical vapor deposition.

17. The method of claim 16, the second resistive switching film being deposited using atomic layer deposition.

18. The method of claim 17, wherein the first resistive switching film comprises hafnium oxide and the second resistive switching film comprises hafnium oxide.

19. The method of claim 1, further comprising annealing a stack comprising the first electrode and the first resistive switching film.

20. The method of claim 1, wherein the annealed stack further comprises a second resistive switching film.