SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20130099292A1
• Filed: 06/30/2011
• Published: 04/25/2013
• Est. Priority Date: 07/01/2010
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakatani, Goro
• Granted Patent: US 8,946,786 B2
• Time in Patent Office: Days
• US Class Current: 257/254
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: G01C 19/5733 Structural details or topology
• CPC Class Codes: G01C 19/5769 Manufacturing; Mounting; Housings
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 2015/0814 for translational movement of the mass, e.g. shuttle type
• CPC Class Codes: G01P 2015/0831 the mass being of the paddle type having the pivot axis between the longitudinal ends of the mass, e.g. see-saw configuration
• CPC Class Codes: G01P 2015/0845 using a plurality of spring-mass systems being arranged on one common planar substrate, the systems not being mechanically coupled and the sensitive direction of each system being different
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 25/071 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor substrate of a semiconductor device has a sensor region and an integrated circuit region, and a cavity is formed immediately under a surface layer portion of the sensor region. A capacitive acceleration sensor is formed on the sensor region by working a surface layer portion of the semiconductor substrate opposed to the cavity. The capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode. A CMIS transistor is formed on the integrated circuit region. The CMIS transistor includes a P-type well region and an N-type well region formed on the surface layer portion of the semiconductor substrate. A gate electrode is opposed to the respective ones of the P-type well region and the N-type well region through a gate insulating film formed on a surface of the semiconductor substrate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a sensor region and an integrated circuit region, with a cavity formed immediately under a surface layer portion of the sensor region;

a capacitive acceleration sensor formed on the sensor region; and

a CMIS transistor formed on the integrated circuit region, wherein

the capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode formed by working the surface layer portion opposed to the cavity to mesh with each other at an interval, and

the CMIS transistor includes an N-type well region formed on a surface layer portion of the semiconductor substrate in the integrated circuit region and having a P-type source region and a P-type drain region, a P-type well region formed on the surface layer portion of the semiconductor substrate in the integrated circuit region and having an N-type source region and an N-type drain region, and a gate electrode opposed to the respective ones of the N-type well region and the P-type well region through a gate insulating film formed on a surface of the semiconductor substrate.

2. The semiconductor device according to claim 1,

wherein

the fixed electrode includes a fixed-side electrode portion insulated from the remaining portion of the fixed electrode by an insulating layer embedded in the surface layer portion of the semiconductor substrate, and

the movable electrode includes a movable-side electrode portion insulated from the remaining portion of the movable electrode by an insulating layer embedded in the surface layer portion of the semiconductor substrate.

3. The semiconductor device according to claim 1,

wherein

the capacitive acceleration sensor includes, assuming that two directions orthogonal to each other along the surface of the semiconductor substrate are an X-axis direction and a Y-axis direction and a direction along the thickness direction of the semiconductor substrate orthogonal to the X-axis and the Y-axis is a Z-axis direction, an X-axis sensor detecting acceleration along the X-axis direction, a Y-axis sensor detecting acceleration along the Y-axis direction and a Z-axis direction detecting acceleration along the Z-axis direction,

each of the X-axis sensor, the Y-axis sensor and the Z-axis sensor includes the fixed electrode and the movable electrode,

an X fixed electrode as the fixed electrode of the X-axis sensor is fixed to the semiconductor substrate, and an X movable electrode as the movable electrode of the X-axis sensor is formed to advance to/retreat from the X fixed electrode along the X-axis direction with respect to the semiconductor substrate,

a Y fixed electrode as the fixed electrode of the Y-axis sensor is fixed to the semiconductor substrate, and a Y movable electrode as the movable electrode of the Y-axis sensor is formed to advance to/retreat from the Y fixed electrode along the Y-axis direction with respect to the semiconductor substrate, and

a Z fixed electrode as the fixed electrode of the Z-axis sensor is fixed to the semiconductor substrate, and a Z movable electrode as the movable electrode of the Z-axis sensor is formed to advance to/retreat from the Z fixed electrode along the Z-axis direction with respect to the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein

the sensor region is arranged on a central portion of the semiconductor substrate, and the integrated circuit region is arranged on a peripheral portion surrounding the sensor region.

5. The semiconductor device according to claim 1, further comprising an interlayer dielectric film stacked on the surface of the semiconductor substrate, wherein

the CMIS transistor has a multilayer interconnection structure having a plurality of layers of transistor wires stacked on the interlayer dielectric film, and

the capacitive acceleration sensor further includes a sensor wire formed on the same layer as the transistor wire formed on any layer of the multilayer interconnection structure and made of the same material as the transistor wire.

6. The semiconductor device according to claim 1, wherein

the capacitive acceleration sensor further includes an insulating film formed on the same layer as the gate insulating film and a sensor wire formed on the insulating film and made of the same material as the gate electrode.

7. The semiconductor device according to claim 1, wherein

the semiconductor substrate is a conductive silicon substrate.

8. A capacitive gyro sensor comprising:

a semiconductor substrate having a cavity therein and having a surface portion on one side and a rear surface portion on another side with respect to the cavity;

a fixed electrode formed on the surface portion of the semiconductor substrate and including a first base portion and a plurality of first electrode portions extending from the first base portion along a surface of the semiconductor substrate and interdigitally arrayed at intervals from one another;

a movable electrode formed on the surface portion of the semiconductor substrate, including a second base portion and a plurality of interdigitally arrayed second electrode portions extending from the second base portion toward spaces between the plurality of first electrode portions and meshing with the first electrode portions at intervals, and vertically movable with respect to the fixed electrode;

a first contact portion formed on an opposed portion of the first base portion opposed to the second electrode portions and insulated from the remaining portion of the first base portion; and

second contact portions formed on forward end portions of the second electrode portions and insulated from the remaining portions of the second electrode portions.

9. The capacitive gyro sensor according to claim 8, wherein

the second electrode portions warp in a direction separating from the cavity to project from a surface of the fixed electrode, or warp in a direction toward a rear surface of the semiconductor substrate to project from a rear surface of the fixed electrode.

10. The capacitive gyro sensor according to claim 8, further comprising a first isolation layer embedded in the first base portion to surround the periphery of the opposed portion of the first base portion for separating the opposed portion from the remaining portion of the first base portion.

11. The capacitive gyro sensor according to claim 8, further comprising a second isolation layer embedded in a portion closer to base end portions of the second electrode portions than the forward end portions for isolating the forward end portions from the remaining portions of the second electrode portions.

12. The capacitive gyro sensor according to claim 8, wherein

the semiconductor substrate is a conductive silicon substrate.

13. A method for manufacturing a semiconductor device by forming a capacitive acceleration sensor on a sensor region of a semiconductor substrate and forming a CMIS (Complementary Metal Insulator Semiconductor) transistor on an integrated circuit region of the semiconductor substrate, comprising the steps of:

forming an N-type well region having a P-type source region and a P-type drain region and a P-type well region having an N-type source region and an N-type drain region on a surface layer portion of the integrated circuit region of the semiconductor substrate by selectively implanting an N-type impurity and a P-type impurity into a surface of the semiconductor substrate;

forming a recess dug down up to an intermediate portion of the semiconductor substrate in the thickness direction thereby simultaneously forming an interdigital fixed electrode and an interdigital movable electrode meshing with each other through the recess by selectively etching a surface layer portion of the sensor region of the semiconductor substrate;

forming a protective film on the inner surface of the recess;

selectively removing the protective film from the bottom surface of the recess; and

forming a cavity by removing lower portions of the fixed electrode and the movable electrode by isotropic etching after digging down the recess by anisotropic etching after the removal of the protective film.

14. The method for manufacturing a semiconductor device according to claim 13, further comprising the steps of:

forming a trench on the surface layer portion of the sensor region of the semiconductor substrate by selectively etching the semiconductor substrate in advance of the formation of the recess; and

forming an insulating layer in the trench by embedding an insulating material in the trench, wherein

the step of forming the recess includes a step of etching the semiconductor substrate so that the fixed electrode and the movable electrode are partially insulated from the remaining portions of the fixed electrode and the movable electrode by the insulating layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein

the step of forming the trench and the step of forming the insulating layer are carried out in advance of the step of forming the N-type well region and the P-type well region.

16. The method for manufacturing a semiconductor device according to claim 13, further comprising the steps of:

stacking an insulating film on the semiconductor substrate; and

selectively depositing a metallic material on the insulating film thereby forming a transistor wire for the CMIS transistor and a sensor wire for the capacitive acceleration sensor on the same layer.

17. The method for manufacturing a semiconductor device according to claim 16, wherein

the step of selectively depositing the metallic material includes a step of depositing the metallic material on regions for forming the fixed electrode and the movable electrode, and

the step of forming the recess includes a step of forming the recess by etching employing a layer including the deposited metallic material as a mask and simultaneously forming the fixed electrode and the movable electrode.