METHOD TO PERFORM ELECTRICAL TESTING AND ASSEMBLY OF ELECTRONIC DEVICES

• US 20130109111A1
• Filed: 12/20/2012
• Published: 05/02/2013
• Est. Priority Date: 08/28/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pagani, Alberto
• Granted Patent: US 8,941,108 B2
• Time in Patent Office: Days
• US Class Current: 438/15
• CPC Class Codes: G01R 31/2818 using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors G01R31/2805 takes precedence; printed circuits having, e.g. symbols, test patterns or visualisation means H05K1/0266
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48147 : with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 : the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49109 : outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package.

Claims

1. A method, comprising:

performing electrical wafer testing and assembly of a first electronic device on a wafer, the first electronic device including an insulating layer on the wafer, a passivation layer covering the insulating layer, and a first pad made in the insulating layer, the performing including;

providing said first electronic device with an extended metallization layer extending on said passivation layer from said first pad to a non-active area of said wafer;

connecting said first electronic device to a testing apparatus;

performing the electrical wafer testing of said first electronic device by positioning a probe of said testing apparatus on a portion of said extended metallization layer positioned on said non-active area;

cutting said wafer after performing the electrical wafer testing of said first electronic device, the cutting including reducing an extension of said metallization layer to an edge of said first electronic device; and

forming on said extended metallization layer an electrical connection after cutting said wafer.

2. The method according to claim 1, further comprising forming an electrically insulating filling layer in the non-active area, the electrically insulating filling layer being positioned between the insulating layer and the extended metallization layer.

3. The method according to claim 1, further comprising realizing said non-active area with a lowered surface with respect to a surface of said first electronic device.

4. The method according to claim 1, further comprising realizing said non-active area with a surface that is level with respect to a surface of said passivation layer.

5. The method according to claim 1, wherein the non-active area includes a scribe line area of the wafer.

6. The method according to claim 1, further comprising forming a second device on the wafer, the second device including a second pad, wherein said extended metallization layer extends from said first pad to the second pad and on said non-active area of said wafer.

7. The method according to claim 1, further comprising forming a blind via extending from said extended metallization layer at one of the following positions:

at an edge of said first electronic device adjacent to said non-active area;

inside an active area of said first electronic device; and

in said non-active area.

8. The method according to claim 1, further comprising forming a through-silicon via in said first electronic device, and in contact with said extended metallization layer, forming the through-silicon via including depositing a layer of metallic material that extends from said first pad vertically through at least part of said first electronic device, wherein said extended metallization layer is formed simultaneously with forming the layer of metallic material.

9. The method according to claim 1, wherein said electrical connection is positioned on a portion of said metallization layer extended to the edge.

10-18. -18. (canceled)

19. A method to perform electrical testing and assembly of a first electronic device comprised in a wafer and including a first pad in an active area of the first electronic device, said pad being surrounded by a dielectric layer which is covered by a passivation layer, the method comprising:

electrically coupling said electronic device to a testing apparatus;

providing said first electronic device with an extended metallization layer extending on said passivation layer from said first pad to a non-active area of said wafer, said non-active area being free of pads;

performing the electrical testing of said electronic device, the performing including positioning a probe of said testing apparatus on a portion of said extended metallization layer on said non-active area, no pads having been realized on said non-active region under said portion;

cutting said wafer, the cutting including reducing an extension of said extended metallization layer to an edge of said first electronic device; and

embedding said first electronic device inside a package and forming on said extended metallization layer an electric connection configured to be connected to a circuit in said package.

20. The method according to claim 19, wherein said non-active area comprises an electrically insulating filling layer.

21. The method according to claim 19, comprising forming said non-active area with a lowered surface with respect to a surface of said first electronic device.

22. The method according to claim 19, comprising forming said non-active area with a surface leveled to a surface of said passivation layer.

23. The method according to claim 19, wherein the non-active area includes a scribe line area of the wafer.

24. The method according to claim 19, wherein said extended metallization layer extends from said first pad to a second pad of a second electronic device of said wafer through said non-active area of said wafer.

25. The method according to claim 19, comprising forming a blind via extending from said extended metallization layer at one of the following positions:

at an edge of said first electronic device adjacent to said non-active area;

inside the active area of said first electronic device;

in said non-active area.

26. The method according to claim 19, further comprising forming a through-silicon via in said first electronic device, and in contact with said extended metallization layer, forming the through-silicon via including depositing a layer of metallic material that extends from said first pad vertically through at least part of said first electronic device, wherein said extended metallization layer is formed simultaneously with forming the layer of metallic material.

27. The method according to claim 19, wherein said electric connection is positioned on a portion of said extended metallization layer which is extended to the edge.