Dynamically Controlling Cache Size To Maximize Energy Efficiency

• US 20130111121A1
• Filed: 10/31/2011
• Published: 05/02/2013
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishnan, Avinash N., Rotem, Efraim, Wiessman, Eliezer, Rajwan, Doron, Shulman, Nadav, Naveh, Alon, Abu-Salah, Hisham
• Granted Patent: US 9,158,693 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/282 Partitioned cache
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Claims

1. A method comprising:

determining, in a power controller of a multicore processor, whether a memory dependency value of a workload is greater than a first threshold, and if so enabling all of a plurality of ways of a cache memory of the multicore processor; and

otherwise determining, in the power controller, if the memory dependency value is less than a third threshold, and if so disabling at least one way of the cache memory.

2. The method of claim 1, further comprising enabling at least one more way of the cache memory if the memory dependency value is greater than a second threshold, the second threshold between the first and second thresholds.

3. The method of claim 1, further comprising enabling all of the plurality of ways of the cache memory if time spent in an active state is greater than a time interval threshold.

4. The method of claim 1, further comprising calculating the memory dependency value of the workload.

5. The method of claim 4, wherein calculating the memory dependency value of the workload includes determining an order buffer residency during a time interval.

6. The method of claim 5, further comprising updating a counter of an entry of an order buffer for each cycle that an outstanding load operation is stored in the order buffer entry.

7. The method of claim 6, further comprising:

determining an average of a plurality of counters, each counter of an entry of the order buffer; and

calculating a ratio between the average and a length of the time interval.

8. The method of claim 7, further comprising controlling a size of the cache memory based at least in part on the ratio.

9. The method of claim 4, wherein calculating the memory dependency value of the workload is based at least in part on a number of miss accesses to the cache memory from at least one core of the multicore processor during a time interval.

10. A processor comprising:

a plurality of cores each to independently execute instructions;

a cache memory coupled to the plurality of cores and including a plurality of partitions; and

a power controller coupled to the plurality of cores and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the plurality of cores.

11. The processor of claim 10, wherein the power controller is to cause at least one of the plurality of partitions to maintain a state of a core when the processor is in a package low power state.

12. The processor of claim 10, wherein the plurality of partitions correspond to ways of the cache memory, and wherein the power controller is to dynamically enable or disable each of the plurality of ways independently.

13. The processor of claim 12, wherein the power controller is to cause at least one way of the cache memory to be enabled with a retention voltage when the processor is in a package low power state.

14. The processor of claim 13, wherein the power controller is to cause at least one way of the cache memory to be disabled when the processor is in the package low power state, wherein the at least one disabled way is to be flushed to a system memory prior to being disabled.

15. The processor of claim 14, wherein the power controller is to power gate the at least one disabled way.

16. A system comprising:

a multicore processor including a plurality of cores, a shared cache, and a first logic to dynamically enable a portion of the shared cache to retain a state of at least one of the plurality of cores when the multicore processor is in a package low power state in which at least one other portion of the shared cache is power gated; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

17. The system of claim 16, wherein the first logic is to dynamically vary a size of the shared cache based on a memory boundedness of a workload executed on at least one of the plurality of cores.

18. The system of claim 17, wherein the shared cache comprises a plurality of ways, and the first logic is to compare a memory dependency value of the workload to at least one threshold and to control the dynamic enabling of the portion of the shared cache to be maintained based on the comparison.

19. The method of claim 18 wherein the first logic is to determine the memory dependency value based at least in part on an order buffer residency during a time interval.

20. The system of claim 18, wherein the first logic is to determine the memory dependency value based at least in part on a number of miss accesses to the shared cache from at least one of the plurality of cores during a time interval.