HARDWARE TASK MANAGER

• US 20130117404A1
• Filed: 06/11/2012
• Published: 05/09/2013
• Est. Priority Date: 06/25/2002
• Status: Active Grant

• Current Assignee: Cornami, Inc.
• Original Assignee: Sviral, Inc.
• Inventors: Scheuermann, W. James, Hogenauer, Eugene B.
• Granted Patent: US 8,782,196 B2
• Time in Patent Office: Days
• US Class Current: 709/212
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/17331 Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared, thereby indicating the input buffer has sufficient data and is available to be processed by a task.

Claims

1-28. -28. (canceled)

29. An integrated circuit comprising:

a plurality of computing nodes, at least one of the plurality computing node comprising memory;

an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes to route data to at least one of the plurality of computing nodes; and

a hardware task manager in the at least one of the plurality of computing nodes, the hardware task manager configured to write input data to a local memory address based on parameters associated with an input port assigned to the data.

30. The integrated circuit of claim 29, wherein the plurality of computing nodes comprise a plurality of heterogeneous computing nodes.

31. The integrated circuit of claim 29, wherein the interconnection network is reconfigurable.

32. The integrated circuit of claim 29, wherein the parameters are selected from the group consisting of counts and triggers.

33. The integrated circuit of claim 29, wherein the hardware task manager is configured to write the data into a buffer in the memory using the parameters associated with the input port.

34. The integrated circuit of claim 29, wherein the buffer is a power-of-2-sized buffer.

35. The integrated circuit of claim 29, wherein the hardware task manager is further configured to indicate that a task is ready to run when all the input data associated with the task is available in the memory.

36. The integrated circuit of claim 29, wherein the hardware task manager is further configured to execute a task when all the input data associated with the task is available in the memory.

37. The integrated circuit of claim 29, wherein the hardware task manager is further configured to add a task to a ready to run queue when all the input data associated with the task is available in the memory.

38. The integrated circuit of claim 29, wherein the hardware task manager is further configured to maintain a port count, the ports count being updated when input data becomes available for a task.

39. The integrated circuit of claim 38, wherein the ports count is updated when input data for the task is in the memory.

40. A method for managing tasks within a computing device having a plurality of computing nodes, at least one computing node comprising a memory, an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes to route data to at least one of the plurality of computing nodes, and a task manager in the at least one of the plurality of computing nodes, the method comprising:

determining parameters associated with an input port assigned to data at the task manager; and

writing the data to a local memory address based on the parameters.

41. The method of claim 40, wherein the plurality of computing nodes comprise a plurality of heterogeneous computing nodes.

42. The method of claim 40, wherein writing the data to a local memory address based on the parameters comprises writing the data into a buffer in the memory using the parameters associated with the input port.

43. The method of claim 40, further comprising indicating that a task is ready to run when all the input data associated with the task is available in the memory.

44. The method of claim 40, further comprising executing a task when all the input data associated with the task is available in the memory.

45. The method of claim 40, further comprising adding a task to a ready to run queue when all the input data associated with the task is available in the memory.

46. The method of claim 40, further comprising maintaining a ports count.

47. The method of claim 46, wherein maintaining the ports count comprises updating the ports count when input data becomes available for a task.

48. The method of claim 46, further comprising updating the ports count when input data for the task is in the memory.