DISTRIBUTING CLOCK ASSOCIATED WITH A WIRED DATA CONNECTION OVER WIRELESS INTERFACES USING FREQUENCY CORRECTION AT THE TRANSMITTER SIDE

• US 20130121436A1
• Filed: 12/25/2012
• Published: 05/16/2013
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Siklu Communication Ltd.
• Original Assignee: Siklu Communication Ltd.
• Inventors: Maysel, Boris, Leiba, Yigal
• Granted Patent: US 8,964,883 B2
• Time in Patent Office: Days
• US Class Current: 375/295
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04L 27/2627 Modulators
• CPC Class Codes: H04L 27/2649 Demodulators
• CPC Class Codes: H04L 7/0091 Transmitter details

Abstract

A clock extractor extracts clock frequency f2, from a wired data connection feeding the transmitter with data clocked at the clock frequency f2. A clock error estimator estimates clock frequency error between the clock frequency f2 and a clock frequency f1 derived from a local clock of the transmitter. Clock adder adds the clock frequency error to the clock frequency f1, resulting in a synthesized clock frequency f2. A modulator uses the synthesized clock frequency f2, to modulate a data stream into a modulated signal.

Claims

1. A method for using a synthesized clock frequency to generate a modulated signal, comprising:

extracting, by a transmitter, clock frequency f2 from a wired data connection feeding the transmitter with data clocked at the clock frequency f2;

estimating clock frequency error between the clock frequency f2 and a clock frequency f1 derived from a local clock of the transmitter;

adding the clock frequency error to the clock frequency f1, resulting in a synthesized clock frequency f2; and

using the synthesized clock frequency f2 to modulate a data stream into a modulated signal.

2. The method of claim 1, wherein adding the clock frequency error to the clock frequency f1 is done using Direct Digital Synthesis (DDS).

3. The method of claim 2, wherein the DDS is a discrete component in the transmitter.

4. The method of claim 1, wherein adding the clock frequency error to the clock frequency f1 is done numerically by a processor.

5. The method of claim 4, wherein the processor is also used to modulate the data.

6. The method of claim 4, wherein adding the clock frequency error to the clock frequency f1 is done using Direct Digital Synthesis (DDS).

7. The method of claim 1, wherein the modulated signal is OFDM, and using the synthesized clock frequency f2 to modulate the data comprises clocking an Inverse Fast Fourier Transform (IFFT) using a clock associated with the synthesized clock frequency f2.

8. The method of claim 1, wherein estimating the clock frequency error between the clock frequency f2 and the clock frequency f1 is done by counting clock cycles of the clock frequency f2 and the clock frequency f1 over a period, and comparing the counts.

9. The method of claim 1, further comprising the step of up-converting the modulated signal into a wireless signal containing the synthesized clock frequency f2.

10. The method of claim 1, wherein the wired data connection feeding the transmitter is an Ethernet wired connection.

11. A method for using a synthesized clock frequency to generate a wireless signal, comprising:

extracting, by a transmitter, clock frequency f2 from a wired data connection feeding the transmitter with data clocked at the clock frequency f2;

estimating clock frequency error between the clock frequency f2 and a clock frequency f1 derived from a local clock of the transmitter;

adding the clock frequency error to the clock frequency f1, resulting in a synthesized clock frequency f2;

modulating a data stream into a modulated signal; and

up-converting, using the synthesized clock frequency f2, the modulated signal into a wireless signal.

12. The method of claim 11, wherein adding the clock frequency error to the clock frequency f1 is done using Direct Digital Synthesis (DDS).

13. The method of claim 12, wherein the DDS is a discrete component in the transmitter.

14. The method of claim 11, wherein adding the clock frequency error to the clock frequency f1 is done numerically by a processor.

15. The method of claim 11, wherein estimating the clock frequency error between the clock frequency f2 and the clock frequency f1 is done by counting clock cycles of the clock frequency f2 and the clock frequency f1 over a period, and comparing the counts.

16. The method of claim 11, further comprising:

reconstructing, by a radio of a receiver, from the wireless signal, the synthesized clock frequency f2 into reconstructed synthesized clock frequency f2; and

clocking a second wired data connection, at the receiver, using the reconstructed synthesized clock frequency f2.

17. The method of claim 16, wherein the extraction is done using a Phase Lock Loop (PLL).

18. A method for using a synthesized clock frequency to generate a modulated signal an up-convert it to a wireless signal, comprising:

extracting, by a transmitter, clock frequency f2 from a wired data connection feeding the transmitter with data clocked at the clock frequency f2;

estimating clock frequency error between the clock frequency f2 and a clock frequency f1 derived from a local clock of the transmitter;

adding the clock frequency error to the clock frequency f1, resulting in a synthesized clock frequency f2;

using the synthesized clock frequency f2 to modulate a data stream into a modulated signal containing the synthesized clock frequency f2; and

up-converting, using the synthesized clock frequency f2, the modulated signal into a wireless signal containing synthesized clock frequency f2.

19. The method of claim 18, wherein the second wired data connection is an Ethernet wired connection.

20. The method of claim 18, wherein the wired data connection feeding the transmitter is an Ethernet wired connection.