MEMORY SUBSYSTEM AND METHOD

• US 20130124904A1
• Filed: 09/14/2012
• Published: 05/16/2013
• Est. Priority Date: 06/23/2008
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Rajan, Suresh Natarajan
• Granted Patent: US 8,762,675 B2
• Time in Patent Office: Days
• US Class Current: 713/401
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.

Claims

1. (canceled)

2. A sub-system comprising:

a plurality of memory devices comprising a first memory device, wherein a timing for a data burst from each of the plurality of memory devices is provided by a respective, different, data strobe (DQS) signal;

an interface circuit comprising;

a plurality of memory data signal interfaces comprising a first memory data signal interface, a number of the plurality of memory data signal interfaces being equal to a number of the plurality of memory devices, each memory data signal interface including a respective data (DQ) path and a respective data strobe (DQS) path coupled to a corresponding memory device of the plurality of memory devices, wherein the first memory data signal interface is coupled to the first memory device;

a system control signal interface coupled to a memory controller, the system control signal interface configured to receive a first read command from the memory controller; and

emulation and command translation logic configured to;

select the first memory data signal interface based on the first read command;

receive a first data burst from the first memory data signal interface, wherein a timing reference for the first data burst is provided by a DQS signal of the first memory device;

delay the first data burst to align a phase difference between the DQS signal of the first memory device and a clock signal of the interface circuit; and

transmit the delayed first data burst to the memory controller.

3. The sub-system of claim 2, wherein

the plurality of memory devices further comprises a second memory device,

the plurality of memory data signal interfaces further comprises a second memory data signal interface,

the system control signal interface is further configured to receive a second read command from the memory controller, and

the emulation and command translation logic is further configured to:

select the second memory data signal interface based on the second read command;

receive a second data burst from the second memory data signal interface, wherein a timing of the second data burst is provided by a DQS signal of the second memory device;

delay the second data burst to align a phase difference between the DQS signal of the second memory device and the clock signal;

combine the delayed first data burst and the delayed second data burst into a contiguous data burst; and

transmit the contiguous data burst to the memory controller.

4. The sub-system of claim 3, wherein the emulation and command translation logic is further configured to:

emulate a virtual memory device using at least the first memory device and the second memory device, wherein a memory capacity of the virtual memory device is equal to a combined memory capacity of the first memory device and the second memory device; and

present the virtual memory device to the memory controller.

5. The sub-system of claim 2, wherein

the interface circuit further comprises initialization and configuration logic, the initialization and configuration logic configured to:

select the first memory data signal interface;

issue a calibration read command, via the first memory data signal interface, to read test data stored at the first memory device;

receive the test data from the first memory device across the first memory data signal interface;

determine the phase difference between the DQS signal of the first memory device and the clock signal based on a timing of the received test data; and

set a delay within the first memory data signal interface corresponding to the first memory device.

6. The sub-system of claim 5, wherein selecting the first memory data signal interface further comprises receiving a calibration request and selecting the first memory data signal interface in response to the received calibration request.

7. The sub-system of claim 2, wherein the interface circuit further comprises data path logic, and wherein the data path logic is configured to concatenate two or more data bursts to eliminate an inter-device command scheduling constraint between the two or more data bursts.

8. The sub-system of claim 7, wherein the inter-device command scheduling constraint includes a rank-to-rank data bus turnaround time or an on-die-termination (ODT) control switching time.

9. An interface circuit comprising:

a plurality of memory data signal interfaces comprising a first memory data signal interface, each memory data signal interface including a respective data (DQ) path and a respective data strobe (DQS) path coupled to a respective, different, memory device;

a system control signal interface coupled to a memory controller, the system control signal interface configured to receive a first read command from the memory controller; and

emulation and command translation logic configured to;

select the first memory data signal interface based on the first read command;

receive a first data burst from the first memory data signal interface, wherein a timing reference for the first data burst is provided by a DQS signal of a memory device coupled to the first memory data signal interface;

delay the first data burst to align a phase difference between the DQS signal of the memory device and a clock signal of the interface circuit; and

transmit the delayed first data burst to the memory controller.

10. The interface circuit of claim 9, wherein

the plurality of memory data signal interfaces further comprises a second memory data signal interface,

the system control signal interface is further configured to receive a second read command from the memory controller, and

the emulation and command translation logic is further configured to:

select the second memory data signal interface based on the second read command;

receive a second data burst from the second memory data signal interface, wherein a timing reference for the second data burst is provided by a DQS signal of a memory device coupled to the second memory data signal interface;

delay the second data burst to align a phase difference between the clock signal and the DQS signal of the memory device coupled to the second memory data signal interface;

combine the delayed first data burst and the delayed second data burst into a contiguous data burst; and

transmit the contiguous data burst to the memory controller.

11. The interface circuit of claim 10, wherein the emulation and command translation logic is further configured to:

emulate a virtual memory device using at least the memory device coupled to the first memory data signal interface and the memory device coupled to the second memory data signal interface, wherein a memory capacity of the virtual memory device is equal to a combined memory capacity of the two memory devices; and

present the virtual memory device to the memory controller.

12. The interface circuit of claim 9, further comprising

initialization and configuration logic, the initialization and configuration logic configured to:

select the first memory data signal interface;

issue a calibration read command, via the first memory data signal interface, to read test data stored at the memory device coupled to the first memory data signal interface;

receive the test data across the first memory data signal interface;

determine the phase difference between the DQS signal of the memory device coupled to the first memory data signal interface and the clock signal based on a timing of the received test data; and

set a delay within the first memory data signal interface corresponding to the memory device coupled to the first memory data signal interface.

13. The interface circuit of claim 12, wherein selecting the first memory data signal interface further comprises receiving a calibration request and selecting the first memory data signal interface in response to the received calibration request.

14. The interface circuit of claim 9 further comprising data path logic, the data path logic configured to concatenate two or more data bursts to eliminate an inter-device command scheduling constraint between the two or more data bursts.

15. The interface circuit of claim 14, wherein the inter-device command scheduling constraint includes a rank-to-rank data bus turnaround time or an on-die-termination (ODT) control switching time.

16. A computer-implemented method, comprising:

receiving, by an interface circuit, a first read command from a memory controller;

selecting a first memory data signal interface of a plurality of memory data signal interfaces based on the first read command;

receiving a second read command from a memory controller;

selecting a second memory data signal interface of the plurality of memory data signal interfaces based on the second read command;

receiving a first data burst from the first memory data signal interface, wherein a timing reference for the first data burst is provided by a first DQS signal of a memory device coupled to the first memory data signal interface;

receiving a second data burst from the second memory data signal interface, wherein a timing reference for the second data burst is provided by a second, different, DQS signal of a memory device coupled to the second memory data signal interface;

delaying the first data burst to align a phase difference between the first DQS signal and a clock signal of the interface circuit;

delaying the second data burst to align a phase difference between the second DQS signal and the clock signal of the interface circuit;

concatenating the delayed first data burst and the delayed second data burst into a contiguous data burst; and

transmitting the contiguous data burst to the memory controller.

17. The method of claim 16, further comprising:

selecting the first memory data signal interface;

issuing a calibration read command, via the first memory data signal interface, to read test data stored at the memory device coupled to the first memory data signal interface;

receiving the test data across the first memory data signal interface;

determining the phase difference between the first DQS signal the clock signal based on a timing of the received test data; and

setting a delay within the first memory data signal interface corresponding to the memory device coupled to the first memory data signal interface.

18. The method of claim 16, further comprising:

emulating a virtual memory device using at least the memory device coupled to the first memory data signal interface and the memory device coupled to the second memory data signal interface, wherein a memory capacity of the virtual memory device is equal to a combined memory capacity of the two memory devices; and

presenting the virtual memory device to the memory controller.

19. The method of claim 16, wherein concatenating the delayed first data burst and the delayed second data burst into a contiguous data burst further comprises concatenating the delayed first data burst and the delayed second data burst into the contiguous data burst to eliminate an inter-device command scheduling constraint between the first data burst and the second data burst.

20. The method of claim 19, wherein the inter-device command scheduling constraint includes a rank-to-rank data bus turnaround time or an on-die-termination (ODT) control switching time.