PIXEL ARRAY AREA OPTIMIZATION USING STACKING SCHEME FOR HYBRID IMAGE SENSOR WITH MINIMAL VERTICAL INTERCONNECTS

• US 20130126707A1
• Filed: 05/14/2012
• Published: 05/23/2013
• Est. Priority Date: 05/12/2011
• Status: Active Grant

• Current Assignee: Depuy Synthes Products Incorporated (Johnson & Johnson)
• Original Assignee: Olive Medical Corporation (Johnson & Johnson)
• Inventors: BLANQUART, Laurent
• Granted Patent: US 9,123,602 B2
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: A61B 1/00009 of image signals during a use of endoscope
• CPC Class Codes: A61B 1/051 Details of CCD assembly
• CPC Class Codes: A61B 1/0676 at distal tip of an endoscope
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 31/028 : including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/0296 : including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe
• CPC Class Codes: H01L 31/0304 : including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H04N 23/555 : for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes
• CPC Class Codes: H04N 23/56 : provided with illuminating means
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 : Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/772 : comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/778 : comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

Claims

1. An imaging sensor comprising:

a plurality of substrates;

a pixel array; and

a plurality of supporting circuits;

wherein a first substrate of the plurality of substrates consists of the pixel array;

wherein the plurality of supporting circuits are disposed on a second, subsequent supporting substrate that is disposed remotely relative to said first substrate;

wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array; and

wherein said second, subsequent supporting substrate is disposed behind said pixel array relative to an object to be imaged.

2. The imaging sensor of claim 1, wherein the pixel array comprises a plurality of pixel columns, each pixel column comprising a plurality of detecting elements, with one pixel column bus per pixel column;

wherein the second, subsequent supporting substrate comprises a plurality of circuit columns with one circuit column bus per circuit column;

wherein each pixel column bus and each circuit column bus are superimposed, such that each pixel column bus and each circuit column bus are substantially aligned; and

wherein at least one interconnect provides an electrical connection between each pixel column bus and each circuit column bus, and wherein the interconnect is placed anywhere along a path of the superimposed pixel column bus and the circuit column bus.

3. The imaging sensor of claim 2, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a single interconnect.

4. The imaging sensor of claim 2, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a two interconnects.

5. The imaging sensor of claim 1, wherein said imaging sensor is backside illuminated.

6. The imaging sensor of claim 1, wherein the plurality of substrates further comprise a plurality of subsequent supporting substrates.

7. The imaging sensor of claim 1, wherein said pixel array covers a substantial majority of a surface of said first substrate.

8. The imaging sensor of claim 1, wherein said pixel array covers more than twenty-five percent of a surface of said first substrate.

9. The imaging sensor of claim 1, wherein one of said supporting circuits is an analog to digital converter.

10. The imaging sensor of claim 1, wherein one of said supporting circuits is an amplifier circuit.

11. The imaging sensor of claim 1, wherein said supporting substrate is aligned with said first substrate in a stacked configuration.

12. The imaging sensor of claim 1, wherein said second, subsequent supporting substrate is disposed behind said first substrate and displaced laterally therefrom.

13. The imaging sensor of claim 5, wherein said first substrate is made of primarily silicon material.

14. The imaging sensor of claim 5, wherein said first substrate is made of primarily of “

High-Z”

semiconductor material, such as Cadmium Telluride.

15. The imaging sensor of claim 5, wherein said first substrate is made of III-V semiconductor materials.

16. The imaging sensor of claim 6, wherein said first substrate and said plurality of subsequent supporting substrates are stacked in alignment so that a plurality of communication columns are formed in a multi-layer stack.

17. An imaging sensor comprising:

a plurality of substrates;

a pixel array; and

a plurality of supporting circuits;

wherein a first substrate of the plurality of substrates comprises the pixel array;

wherein the plurality of supporting circuits are disposed on a second, subsequent supporting substrate that is disposed remotely relative to said first substrate;

wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array;

wherein said second, subsequent supporting substrate is disposed behind said pixel array relative to an object to be imaged; and

wherein said pixel array covers a majority of a first surface of said first substrate.

18. The imaging sensor of claim 17, wherein the pixel array comprises a plurality of pixel columns, each pixel column comprising a plurality of detecting elements, with one pixel column bus per pixel column;

wherein the second, subsequent supporting substrate comprises a plurality of circuit columns with one circuit column bus per circuit column;

wherein each pixel column bus and each circuit column bus are superimposed, such that each pixel column bus and each circuit column bus are substantially aligned; and

wherein at least one interconnect provides an electrical connection between each pixel column bus and each circuit column bus, and wherein the interconnect is placed anywhere along a path of the superimposed pixel column bus and the circuit column bus.

19. The imaging sensor of claim 18, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a single interconnect.

20. The imaging sensor of claim 18, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a two interconnects.

21. The imaging sensor of claim 17, wherein said imaging sensor is backside illuminated.

22. The imaging sensor of claim 17, wherein the plurality of substrates further comprise a plurality of subsequent supporting substrates.

23. The imaging sensor of claim 17, wherein said pixel array covers more than fifty-five percent of a surface of said first substrate.

24. The imaging sensor of claim 17, wherein one of said supporting circuits is an analog to digital converter.

25. The imaging sensor of claim 17, wherein one of said supporting circuits is an amplifier circuit.

26. The imaging sensor of claim 17, wherein said supporting substrate is aligned with said first substrate.

27. The imaging sensor of claim 17, wherein said supporting substrate is disposed behind said first substrate and displaced laterally therefrom.

28. The imaging sensor of claim 21, wherein said first substrate is made of primarily silicon material.

29. The imaging sensor of claim 21, wherein said first substrate is made of primarily of “

High-Z”

semiconductor material, such as Cadmium Telluride.

30. The imaging sensor of claim 21, wherein said first substrate is made of III-V semiconductor materials.

31. The imaging sensor of claim 22, wherein said first substrate and said plurality of subsequent supporting substrates are stacked in alignment so that a plurality of communication columns are formed in a multi-layer stack.

32. An imaging sensor comprising:

a plurality of substrates;

a pixel array; and

a plurality of supporting circuits;

wherein a first substrate of the plurality of substrates comprises the pixel array;

wherein the plurality of supporting circuits are disposed on at least one subsequent supporting substrate that is disposed remotely relative to said first substrate;

wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array;

wherein said at least one subsequent supporting substrates is disposed behind said pixel array relative to an object to be imaged; and

wherein said pixel array covers at least forty percent of a first surface of said first substrate;

wherein the pixel array of said first substrate electrically communicates with the plurality of supporting circuits disposed on said at least one subsequent supporting substrate through a plurality of respective read-buses disposed on each of the plurality of substrates and are electronically connected through interconnects.

33. The imaging sensor of claim 32, wherein the pixel array comprises a plurality of pixel columns, each pixel column comprising a plurality of detecting elements, with one pixel column bus per pixel column;

wherein the second, subsequent supporting substrate comprises a plurality of circuit columns with one circuit column bus per circuit column;

wherein each pixel column bus and each circuit column bus are superimposed, such that each pixel column bus and each circuit column bus are substantially aligned; and

wherein an interconnect provides an electrical connection between each pixel column bus and each circuit column bus, and wherein the interconnect is placed anywhere along a path of the superimposed pixel column bus and the circuit column bus.

34. The imaging sensor of claim 33, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a single interconnect.

35. The imaging sensor of claim 33, wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a two interconnects.

36. The imaging sensor of claim 32, wherein said imaging sensor is backside illuminated.

37. The imaging sensor of claim 32, wherein the at least one subsequent supporting substrate comprises a plurality of subsequent supporting substrates.

38. The imaging sensor of claim 32, wherein said pixel array covers a substantial majority of a surface of said first substrate.

39. The imaging sensor of claim 32, wherein said pixel array covers more than fifty percent of a surface of said first substrate.

40. The imaging sensor of claim 32, wherein one of said plurality of supporting circuits is an analog to digital converter.

41. The imaging sensor of claim 32, wherein one of said supporting circuits is an amplifier circuit.

42. The imaging sensor of claim 32, wherein said at least one subsequent supporting substrate is aligned with said first substrate.

43. The imaging sensor of claim 32, wherein said at least one subsequent supporting substrate is disposed behind said first substrate and displaced laterally therefrom.

44. The imaging sensor of claim 36, wherein said first substrate is made of primarily silicon material.

45. The imaging sensor of claim 36, wherein said first substrate is made of primarily of “

High-Z”

semiconductor material, such as Cadmium Telluride.

46. The imaging sensor of claim 36, wherein said first substrate is made III-V semiconductor materials.

47. The imaging sensor of claim 37, wherein said first substrate and said plurality of subsequent supporting substrates are stacked in alignment so that a plurality of communication columns are formed in a multi-layer stack.

48. An imaging sensor comprising:

a plurality of substrates comprising at least a first substrate and a second substrate;

a pixel array located on the first substrate and comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is defined as one pixel in width and a plurality of pixels in length;

a plurality of supporting circuits located on the second substrate and comprising a plurality of circuit columns, where one circuit column corresponds with one pixel column, wherein each of the plurality of circuit columns is defined as having an area that corresponds with an area of a corresponding pixel column;

a plurality of buses, wherein there is one pixel column bus per pixel column residing on the first substrate and one circuit column bus per circuit column residing on said second substrate;

wherein at least a portion of each of the pixel column buses is superimposed with at least a portion of each of the corresponding circuit column buses;

at least one interconnect providing electrical communication between one pixel column bus and one corresponding circuit column bus; and

wherein said at least one interconnect is located anywhere between one pixel column bus and one corresponding circuit column bus and are superimposed with respect to each other.

49. The imaging sensor of claim 48, wherein the first substrate and second substrate are in alignment.

50. The imaging sensor of claim 48, wherein an area of one of said pixel columns on said first substrate is substantially equal to an area of one of said corresponding circuit columns on said second substrate.

51. The imaging sensor of claim 48, wherein said second substrate is substantially the same size as said first substrate.

52. The imaging sensor of claim 48, wherein an area of one of said pixel columns on said first substrate is larger than an area of one of said corresponding circuit columns on said second substrate.

53. The imaging sensor of claim 48, wherein an area of one of said pixel columns on said first substrate is smaller than an area of one of said corresponding circuit columns on said second substrate.

54. The imaging sensor of claim 48, wherein an aspect ratio of one of said pixel columns is substantially similar to an aspect ratio of one of said circuit columns.

55. The imaging sensor of claim 48, wherein a plurality of interconnects connect a pixel column bus to a corresponding circuit column bus.

56. The imaging sensor of claim 48, wherein an aspect ratio of one of said pixel columns is different than an aspect ratio of one of said circuit columns.

57. The imaging sensor of claim 56, wherein the aspect ratio of one of said circuit columns is four times wider than and one-fourth the length of the aspect ratio of one of said pixel columns.

58. The imaging sensor of claim 56, wherein the aspect ratio of one of said circuit columns is two times wider than and one-half the length of the aspect ratio of one of said pixel columns.

59. The imaging sensor of claim 49, wherein, said first substrate is made of primarily silicon material.

60. The imaging sensor of claim 49, wherein said first substrate is made of primarily of “

High-Z”

semiconductor material, such as Cadmium Telluride.

61. The imaging sensor of claim 49, wherein said first substrate is made III-V semiconductor materials.

62. The imaging sensor of claim 49, wherein there is two-way shared pixel architecture, where there is one pixel column bus for every two, adjacent pixel columns.