SEMICONDUCTOR APPARATUS

• US 20130130496A1
• Filed: 01/16/2013
• Published: 05/23/2013
• Est. Priority Date: 03/15/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: NI, Chyi-Tsong, WANG, I-Shi, LEE, Hsin-Kuei, SU, Ching-Hou
• Granted Patent: US 9,368,390 B2
• Time in Patent Office: Days
• US Class Current: 438/655
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/11826 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11827 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11848 Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13562 On the entire exposed surface of the core
• CPC Class Codes: H01L 2224/13582 Two-layer coating
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/13624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/13666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/165 : Material
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/29599 : Material
• CPC Class Codes: H01L 2224/81011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/81097 : Heating
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/8121 : using a reflow oven
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/81948 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A method for fabricating a semiconductor apparatus including providing a first silicon substrate having a first contact, wherein providing the first silicon substrate comprises forming a silicide layer between the first silicon substrate and a first metal layer. The method further includes providing a second silicon substrate having a second contact comprising a second metal layer and placing the first contact in contact with the second contact. The method further includes heating the first and second metal layers to form a metallic alloy, whereby the metallic alloy bonds the first contact to the second contact.

Claims

1. A method for fabricating a semiconductor apparatus comprising:

providing a first silicon substrate having a first contact, wherein providing the first silicon substrate comprises forming a silicide layer between the first silicon substrate and a first metal layer;

providing a second silicon substrate having a second contact comprising a second metal layer;

placing the first contact in contact with the second contact; and

heating the first and second metal layers to form a metallic alloy, whereby the metallic alloy bonds the first contact to the second contact.

2. The method of claim 1, wherein the heating is performed at a temperature of about 450°

to 500°

C.

3. The method of claim 1, wherein the heating is performed under a compressive force of about 45 to 55 kN.

4. The method of claim 1, wherein forming the silicide layer comprises reacting the first silicon substrate and first metal layer.

5. The method of claim 1, wherein forming the silicide layer is performed at a temperature of about 650°

to 900°

C.

6. The method of claim 1, wherein providing the first silicon substrate comprises defining a width of the first contact, wherein the width of the first contact ranges from 30 micrometers (μ

m) to 80 μ

m.

7. The method of claim 6, wherein providing the second silicon substrate comprises defining a width of the second contact, wherein a ratio of the width of the first contact to a width of the second contact ranges from 0.12 to 1.2.

8. The method of claim 1, further comprising cleaning a surface of the second contact by exposing the surface to a reduction gas prior to placing the first contact in contact with the second contact.

9. The method of claim 1, wherein forming the metal alloy comprises forming a metal alloy having a thickness ranging from 500 Angstroms (Å

) to 1500 Å

.

10. The method of claim 1, wherein providing the first silicon substrate comprises defining at least one raised portion on a surface of the first silicon substrate, wherein the silicide layer and the first metal layer are over the at least one raised portion.

11. A method of fabricating a semiconductor device, the method comprising:

depositing a first metal layer over a first substrate;

annealing the first substrate to form a silicide layer between the first metal layer and the first substrate;

defining a first contact comprising on the first metal layer and the silicide layer;

depositing a second metal layer over a second substrate;

defining a second contact comprising the second metal layer;

pressing the first contact to the second contact; and

heating the first contact and second contact to form a metallic alloy between the first contact and the second contact.

12. The method of claim 11, wherein the heating is performed by annealing the first contact and the second contact at a plurality of temperatures.

13. The method of claim 11, further comprising defining at least one raised portion on a surface of the first substrate.

14. The method of claim 11, further comprising cleaning a surface of the second contact by exposing the surface to a reduction gas prior to pressing the first contact to the second contact.

15. The method of claim 14, wherein exposing the surface to reduction gases comprises exposing the surface to at least one of hydrogen or ammonia.

16. The method of claim 11, wherein forming the metallic alloy comprises forming an alloy comprising aluminum.

17. The method of claim 11, wherein heating the first and second contact comprises performing an annealing process at a temperature ranging from about 450°

C. to about 500°

C.

18. The method of claim 11, wherein pressing the first contact to the second contact comprises exerting a force ranging from about 45 kiloNewtons (kN) to about 55 kN.

19. The method of claim 11, wherein annealing the first substrate to form the silicide layer comprises annealing the first substrate at a temperature ranging from about 650°

C. to about 900°

C.

20. A method of fabricating a semiconductor device, the method comprising:

defining a plurality of first contacts, wherein each first contact of the plurality of first contacts comprises;

at least one raised portion on a surface of a first substrate;

a silicide layer over the at least one raised portion; and

a first metal layer over the at least one raised portion;

defining a plurality of second contacts, wherein each second contact of the plurality of second contacts comprises a second metal layer over a second substrate;

pressing each first contact of the plurality of first contacts to a respective second contact of the plurality of second contacts; and

heating the plurality of first contacts and the plurality of second contacts to form a metallic alloy between each of the first contacts of the plurality of first contacts pressed to the respective second contacts of the plurality of second contacts.