SEMICONDUCTOR STRUCTURE HAVING A POLYSILICON STRUCTURE AND METHOD OF FORMING SAME

• US 20130146993A1
• Filed: 12/08/2011
• Published: 06/13/2013
• Est. Priority Date: 12/08/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHEN, Ryan Chia-Jen, CHANG, Che-Cheng, WU, Po-chi, FANG, Buh-Kuan, LIN, Jr-Jung
• Granted Patent: US 8,574,989 B2
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 21/02071 the processing being a delineation, e.g. RIE, of conductive layers
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.

Claims

1. A method of forming a semiconductor structure comprising:

forming a polysilicon layer over a substrate;

forming a mask layer over the polysilicon layer;

patterning the mask layer to form a patterned mask layer; and

forming a polysilicon structure by etching the polysilicon layer using the patterned mask layer as a mask,

the polysilicon structure having an upper surface and a lower surface, and the etching of the polysilicon layer being arranged to cause a width of the upper surface of the polysilicon structure to be greater than that of the lower surface of the polysilicon structure.

2. The method of claim 1, wherein polysilicon structure has a sidewall, and the sidewall and the lower surface of the polysilicon structure define a sidewall angle which ranges from about 90 degrees to about 110 degrees.

3. The method of claim 1, wherein the etching of the polysilicon layer comprises performing a dry etching in an environment having Cl₂ gas and CF₄ gas.

4. The method of claim 3, wherein the etching of the polysilicon layer has a ratio of the Cl₂ gas to the CF₄ gas greater than a predetermined threshold value.

5. The method of claim 1, wherein the etching of the polysilicon layer comprises performing a wet cleaning for a predetermined period of time ranging from about 5 to about 50 seconds.

6. The method of claim 1, further comprising:

forming a dielectric layer over the substrate and surrounding the polysilicon structure.

7. The method of claim 6, wherein an upper surface of the dielectric layer is coplanar with the upper surface of the polysilicon structure.

8. The method of claim 6, wherein the forming the dielectric layer is arranged to cause the dielectric layer to have a stress level that provides no stress or a tensile stress on a sidewall of the polysilicon structure.

9. A method of forming a semiconductor structure comprising:

forming a polysilicon layer over a substrate;

patterning the polysilicon layer to form a polysilicon structure;

forming a dielectric layer over the substrate and surrounding the polysilicon structure; and

removing the polysilicon structure to form an opening in the dielectric layer,

the opening having a bottom portion and a top portion, and a width of the top portion being greater than that of the bottom portion.

10. The method of claim 9, wherein the opening having a sidewall, and the bottom portion and the sidewall of the opening define a sidewall angle which ranges from about 90 degrees to about 110 degrees.

11. The method of claim 9, wherein the patterning of the polysilicon layer comprises performing a dry etching in an environment having Cl₂ gas and CF₄ gas.

12. The method of claim 11, wherein the etching of the polysilicon layer has a ratio of the Cl₂ gas to the CF₄ gas greater than a predetermined threshold value.

13. The method of claim 9, wherein the removal of the polysilicon structure comprises performing a wet cleaning for a predetermined period of time ranging from about 30 to about 200 seconds.

14. The method of claim 9, wherein the forming the dielectric layer is arranged to cause the dielectric layer to have a stress level that provides no stress or a tensile stress on a sidewall of the polysilicon structure.

15. The method of claim 9, further comprising rounding corners of the dielectric layer at the opening to enlarge a ratio of the width of the top portion of the opening to that of the bottom portion of the opening.

16. A semiconductor structure comprising:

a substrate;

a polysilicon structure formed over the substrate; and

a patterned mask layer formed over the polysilicon structure,

the polysilicon structure having an upper surface and a lower surface, and a width of the upper surface of the polysilicon structure being greater than that of the lower surface of the polysilicon structure.

17. The semiconductor structure of claim 16, wherein the polysilicon structure has a sidewall, and the bottom surface and the sidewall of the polysilicon structure define a sidewall angle ranging from about 90 degrees to about 110 degrees.

18. The semiconductor structure of claim 16, further comprising:

a dielectric layer over the substrate and surrounding the polysilicon structure, the dielectric layer being arranged to have a stress level that provides no stress or a tensile stress on a sidewall of the polysilicon structure.

19. The semiconductor structure of claim 16, further comprising:

a gate dielectric layer formed over the substrate and under the polysilicon structure.

20. The semiconductor structure of claim 16, wherein the mask layer comprises:

a silicon nitride layer formed over the polysilicon structure; and

a silicon oxide layer formed over the silicon nitride layer.