Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating
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Accused Products
Abstract
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.
125 Citations
53 Claims
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1-33. -33. (canceled)
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34. A semiconductor memory cell comprising:
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a floating body region; a floating gate or trapping layer positioned above and insulated from said floating body region; wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said floating gate or trapping layer, upon restoration of power to said memory cell. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41)
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42. A semiconductor memory cell comprising:
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a floating body region; and a floating gate or trapping layer positioned above and insulated from said floating body region; wherein charge flow into said floating body region upon restoration of power to said memory cell depends on charge stored in said floating gate or trapping layer. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49)
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50. A method of operating a semiconductor memory cell, said method comprising:
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providing the memory cell to have a floating body for storing data as volatile memory and a floating gate or trapping layer for storing data as non-volatile memory; and transferring the data stored in the floating gate or trapping layer to the floating body when power is restored to the memory cell. - View Dependent Claims (51, 52, 53)
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Specification