METHOD AND APPARATUS FOR PREVENTING UNAUTHORIZED ACCESS TO INFORMATION STORED IN A NON-VOLATILE MEMORY

• US 20130152206A1
• Filed: 12/07/2011
• Published: 06/13/2013
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: OWL Cyber Defense Solutions LLC
• Original Assignee: Owl Computing Technologies, Inc.
• Inventors: Staubly, Steven
• Granted Patent: US 8,646,094 B2
• Time in Patent Office: Days
• US Class Current: 726/26
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen

Abstract

A communications device for ensuring secure data transfer provided having an interface device for controlling data transfer, an integrated circuit coupled to the interface device and having a processor, a non-volatile memory for storing at least program code for the processor, a volatile memory, an input pin and an output pin; and an electrical conductor which electrically connects the input pin and the output pin. The electrical conductor passes through an external portion of the enclosure, e.g., a slot, which allows a user to easily sever the electrical conductor. In operation, a portion of the program code detects when the electrical conductor is severed and causes the program code in the non-volatile memory to be erased, data transfer via the interface device to be disabled, and power to the integrated circuit cut off to ensure that all information in volatile memory is erased.

Claims

1. A communications device for ensuring secure data transfer, the communications device provided in an enclosure, comprising:

an interface device for controlling data transfer;

an integrated circuit coupled to the interface device and having a processor, a non-volatile memory for storing at least program code for the processor, a volatile memory, an input pin and an output pin;

an electrical conductor which electrically connects the input pin and the output pin, wherein the electrical conductor is positioned in an externally accessible portion of the enclosure to allow a user to easily sever the electrical conductor; and

wherein a portion of the program code detects when the electrical conductor is severed and causes the program code in the non-volatile memory to be erased.

2. The communications device of claim 1, wherein data transfer via the interface device may be selectively disabled and wherein a portion of the program code, upon detection that the electrical conductor has become severed, signals the interface device to disable data transfer.

3. The communications device of claim 1, wherein power for the integrated circuit is selectively provided via the interface device and wherein the program code for the integrated circuit signals the interface controller that erasure of the non-volatile memory is complete and, in response, the interface controller disconnects power to the integrated circuit such that all information in volatile memory is erased.

4. The communications device of claim 1, wherein the externally accessible portion of the enclosure comprises a narrow slot.

5. The communications device of claim 1, wherein the electrical conductor comprises a first conductor portion and a second conductor portion removably affixed to the first conductor portion and wherein the electrical conductor is severed by the user removing the second conductor portion.

6. The communications device of claim 1, wherein the program code implements a data filtering algorithm on data being transferred.

7. The communications device of claim 1, wherein the program code implements a security policy which prevents unauthorized use of the device.

8. The communications device of claim 1, wherein the interface device and the integrated circuit are positioned within a send only circuit portion, wherein the interface device is coupled to a low security host and further comprising:

a second interface device for controlling data transfer to a high security host;

a second integrated circuit coupled to the second interface device and having a processor, a non-volatile memory for storing at least program code for the processor, a volatile memory, an input pin and an output pin;

a second electrical conductor which electrically connects the input pin and the output pin on the second integrated circuit, wherein the electrical conductor is positioned in an externally accessible portion of the enclosure to allow a user to easily sever the second electrical conductor; and

wherein a portion of the program code in the second integrated circuit detects when the second electrical conductor is severed and causes the program code in the non-volatile memory in the second integrated circuit to be erased;

wherein the second interface device and the second integrated circuit are positioned within a receive-only circuit portion.

9. The communications device of claim 8, further comprising a one-way data link coupling the send-only circuit portion to the receive-only circuit portion.

10. The communications device of claim 9, wherein the one-way data link comprises a data-diode.

11. The communications device of claim 9, wherein the one-way data link comprises an optical emitter in the send-only circuit portion, a photo detector in the receive-only circuit portion and an optical link coupling the optical emitter and the photo detector which passes from the send-only circuit portion to the receive-only circuit portion.

12. A method of ensuring secure data transfer, comprising:

passing data from a send-only interface to a receive-only interface under the control of program code running on a processor in an integrated circuit, the program code stored in non-volatile memory in the integrated circuit;

detecting when an electrical conductor coupled to input and output pins on the integrated circuit is severed;

upon detection of the severing of the electrical conductor, causing the program code stored in non-volatile memory to be erased and passing of data to be halted; and

upon completion of erasure of the program code in the non-volatile memory, causing power to be removed from the integrated circuit, thereby erasing all information stored in a volatile memory in the integrated circuit.