DELTA-SIGMA MODULATOR, INTEGRATOR, AND WIRELESS COMMUNICATION DEVICE

• US 20130169460A1
• Filed: 02/27/2013
• Published: 07/04/2013
• Est. Priority Date: 09/07/2010
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: MATSUKAWA, Kazuo, MITANI, Yosuke, DOSHO, Shiro, OBATA, Koji
• Granted Patent: US 8,937,567 B2
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier
• CPC Class Codes: H03M 3/438 the modulator having a higher order loop filter in the feedforward path
• CPC Class Codes: H03M 3/50 Digital/analogue converters using delta-sigma modulation as an intermediate step digital delta-sigma modulators per se H03M7/3004

Abstract

A delta-sigma modulator includes: an integrator having an operational amplifier; a quantizer quantizing an output of the integrator; a first D-A converter converting an output of the quantizer to a current signal to provide negative feedback to the operational amplifier; a feedforward path feeding forward an input of the integrator to the quantizer; and a second D-A converter converting the output of the quantizer to a current signal to provide negative feedback to the quantizer. The integrator includes a resistive element having a first end connected to the input of the integrator and a second end connected to an inverting input of the operational amplifier, n capacitive circuits connected in series between the inverting input and an output of the operational amplifier, and (n−1) resistive elements each having a first end connected to an interconnecting node of the capacitive circuits and a second end connected to a common node.

Claims

1. A delta-sigma modulator, comprising:

an integrator including an operational amplifier;

a quantizer configured to quantize an output of the integrator;

a first D-A converter configured to convert a digital output of the quantizer to a current signal to provide negative feedback to an inverting input end of the operational amplifier;

a feedforward path configured to feed forward an input signal of the integrator to an input end of the quantizer; and

a second D-A converter configured to convert the digital output of the quantizer to a current signal to provide negative feedback to the input end of the quantizer, wherein

the integrator includes

a resistive element having a first end connected to the input signal of the integrator and a second end connected to the inverting input end of the operational amplifier,

n capacitive circuits connected in series between the inverting input end and an output end of the operational amplifier, “

n”

representing an integer of 2 or more, and

(n−

1) resistive elements each having a first end connected to an interconnecting node of the capacitive circuits and a second end connected to a common node.

2. The delta-sigma modulator of claim 1, further comprising:

a switch circuit configured to allow to short-circuit the inverting input end, a non-inverting input end, and the output end of the operational amplifier and the common node.

4. The delta-sigma modulator of claim 1, wherein

at least one of the n capacitive circuits includes a capacitive element and a resistive element which are connected in series.

6. The delta-sigma modulator of claim 4, wherein

at least one of the n capacitive circuits includes a capacitive element connected in parallel to the capacitive element and the resistive element which are connected in series.

10. A wireless communication device, comprising:

the delta-sigma modulator of claim 1; and

a digital baseband processing portion configured to process an output of the delta-sigma modulator.

3. A delta-sigma modulator, comprising:

an integrator including an operational amplifier;

a quantizer configured to quantize an output of the integrator;

a D-A converter configured to convert a digital output of the quantizer to a current signal to provide negative feedback to an inverting input end of the operational amplifier; and

a switch circuit configured to allow to short-circuit the inverting input end, a non-inverting input end, and an output end of the operational amplifier and a common node, wherein

the integrator includes

a resistive element having a first end connected to an input signal of the integrator and a second end connected to the inverting input end of the operational amplifier,

n capacitive circuits connected in series between the inverting input end and the output end of the operational amplifier, “

n”

representing an integer of 2 or more, and

(n−

1) resistive elements each having a first end connected to an interconnecting node of the capacitive circuits and a second end connected to the common node.

5. The delta-sigma modulator of claim 3, wherein

at least one of the n capacitive circuits includes a capacitive element and a resistive element which are connected in series.

7. The delta-sigma modulator of claim 5, wherein

at least one of the n capacitive circuits includes a capacitive element connected in parallel to the capacitive element and the resistive element which are connected in series.

11. A wireless communication device, comprising:

the delta-sigma modulator of claim 3; and

a digital baseband processing portion configured to process an output of the delta-sigma modulator.

8. An integrator having an operational amplifier, comprising:

a resistive element having a first end connected to an input signal of the integrator and a second end connected to an inverting input end of the operational amplifier;

n capacitive circuits connected in series between the inverting input end and an output end of the operational amplifier, “

n”

representing an integer of 2 or more; and

(n−

1) resistive elements each having a first end connected to an interconnecting node of the capacitive circuits and a second end connected to a common node, wherein

at least one of the n capacitive circuits includes a capacitive element and a resistive element which are connected in series.

9. The integrator of claim 8, wherein

at least one of the n capacitive circuits includes a capacitive element connected in parallel to the capacitive element and the resistive element which are connected in series.