IMAGE PROCESSING DEVICE, IMAGE CODING METHOD, AND IMAGE PROCESSING METHOD

• US 20130188723A1
• Filed: 10/03/2011
• Published: 07/25/2013
• Est. Priority Date: 10/04/2010
• Status: Active Grant

• Current Assignee: Sovereign Peak Ventures, LLC (Dominion Harbor Enterprises, LLC)
• Original Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Inventors: Tanaka, Takeshi, Amano, Hiroshi
• Granted Patent: US 9,414,059 B2
• Time in Patent Office: Days
• US Class Current: 375/240.16
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/503 involving temporal prediction adaptive coding with adaptive selection between spatial and temporal predictive coding H04N19/107; adaptive coding with adaptive selection among a plurality of temporal predictive coding modes H04N19/109
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

Provided is an image processing device which performs plural processes efficiently, by pipelining, on a coded stream obtained by coding an image based on various coding unit blocks. The image processing device which performs plural first processes, by pipelining, on a coded stream obtained by dividing an image into plural coding unit blocks having at least two sizes, and coding the image on a coding unit block-by-block basis includes: plural first process units which perform, by the pipelining, the plural first processes on the coded stream by each executing one of the plural first processes; and a control unit which divides the coded stream into plural first processing unit blocks each having a first size, and control the plural first process units to cause the plural first processes to be executed for each of the first processing unit blocks.

Claims

1. An image processing device which performs plural first processes, by pipelining, on a coded stream obtained by dividing an image into plural coding unit blocks having at least two sizes and coding the image on a coding unit block-by-block basis, the image processing device comprising:

plural first process units configured to perform, by the pipelining, the plural first processes on the coded stream by each executing one of the plural first processes; and

a control unit configured to divide or connect portions of the coded stream into plural first processing unit blocks each having a first size, and control the plural first process units to cause the plural first processes to be executed for each of the first processing unit blocks.

2. The image processing device according to claim 1,

wherein the plural first process units are configured to perform, on the coded stream, the plural first processes for decoding the image.

3. The image processing device according to claim 1,

wherein the control unit is configured to divide or connect the portions of the coded stream into the plural first processing unit blocks by dividing a coding unit block included in the coded stream or uniting at least two coding unit blocks included in the coded stream, and control the plural first process units to cause the plural first processes to be executed for each of the first processing unit blocks.

4. The image processing device according to claim 1,

wherein the control unit is configured to control the plural first process units to cause each of the plural first processes to be executed on each of the plural first processing unit blocks in a predetermined period.

5. The image processing device according to claim 1,

wherein the control unit is configured to divide or connect the portions of the coded stream into the plural first processing unit blocks, and control the plural first process units to cause the plural first processes to be executed for each of the first processing unit blocks, the coded stream being obtained by dividing the image into the plural coding unit blocks which are smallest units for each of which inter prediction and intra prediction are switchable, and coding the image on the coding unit block-by-block basis.

6. The image processing device according to claim 1,

wherein the control unit is configured to divide or connect the portions of the coded stream into the plural first processing unit blocks each having the first size predetermined to be a size of a largest coding unit block, and control the plural first process units to cause the plural first processes to be executed for each of the first processing unit blocks.

7. The image processing device according to claim 6,

wherein the control unit is configured to divide or connect the portions of the coded stream into the plural first processing unit blocks each having the first size predetermined to be a size of a largest coding unit which is the largest coding unit block, and control the plural first process units to cause the plural first processes to be executed for each of the first processing unit blocks.

8. The image processing device according to claim 1,

wherein the control unit is configured to divide or connect the portions of the coded stream into the plural first processing unit blocks each having the first size predetermined to be a size of a largest frequency transform block, and control the plural first process units to cause the plural first processes to be executed for each of the first processing unit blocks.

9. The image processing device according to claim 1,

wherein the plural first process units include plural second process units configured to execute plural second processes included in the plural first processes, and

the control unit is configured to divide the plural first processing unit blocks into plural second processing unit blocks each having a second size smaller than the first size, and control the plural second process units to cause the plural second processes to be executed for each of the second processing unit blocks.

10. The image processing device according to claim 1,

wherein the plural first process units include plural second process units configured to execute plural second processes included in the plural first processes, and

the control unit is configured to divide the plural first processing unit blocks into plural second processing unit blocks each having a size equal to or smaller than the first size, and control the plural second process units to cause the plural second processes to be executed for each of the second processing unit blocks.

11. The image processing device according to claim 10,

wherein the control unit is configured to divide the plural first processing unit blocks into the plural second processing unit blocks to separate luma information and chroma information, and control the plural second process units to cause the plural second processes to be executed for each of the second processing unit blocks.

12. The image processing device according to claim 11,

wherein the plural first process units include a motion compensation process unit configured to execute a motion compensation process,

the control unit is configured to divide the plural first processing unit blocks into plural third processing unit blocks each having a third size smaller than the first size, and control the motion compensation process unit to cause the motion compensation process to be executed for each of the third processing unit blocks, and

the control unit is configured to divide the plural first processing unit blocks into the plural third processing unit blocks each including the luma information and the chroma information.

13. The image processing device according to claim 8,

wherein the plural first process units include a motion compensation process unit configured to execute a motion compensation process, and

when a prediction block to be used for the motion compensation process has a size larger than the first size, the control unit is configured to divide the prediction block into the plural first processing unit blocks, and control the motion compensation process unit to cause the motion compensation process to be executed for each of the first processing unit blocks.

14. The image processing device according to claim 8,

wherein the plural first process units include an intra prediction process unit configured to execute an intra prediction process, and

when a prediction block to be used for the intra prediction process has a size larger than the first size, the control unit is configured to divide the prediction block into the plural first processing unit blocks, and control the intra prediction process unit to cause the intra prediction process to be executed for each of the first processing unit blocks.

15. The image processing device according to claim 8,

wherein the plural first process units include a deblocking filtering process unit configured to execute a deblocking filtering process for eliminating coding distortion at a block boundary, and

the control unit is configured to control the deblocking filtering process unit to cause the deblocking filtering process to be executed for each of frequency transform blocks according to order in which a frequency transform process has been executed when the image is coded.

16. An image coding method for coding an image, the method comprising:

dividing the image into plural coding unit blocks having at least two sizes, and executing coding processing on the image on a coding unit block-by-block basis; and

executing a deblocking filtering process on one of a vertical boundary and a horizontal boundary and thereafter on the other of the vertical boundary and the horizontal boundary, on a predetermined data unit-by-unit basis different from the coding unit block-by-block basis, the deblocking filtering process being for eliminating coding distortion at a block boundary included in the image on which the coding processing has been executed.

17. An image coding method for coding an image, the method comprising:

dividing the image into plural coding unit blocks having at least two sizes, and executing coding processing on the image on a coding unit block-by-block basis; and

executing a deblocking filtering process for eliminating coding distortion at a block boundary on the coding unit block-by-block basis according to order in which the coding processing has been executed on the image.

18. An image coding method for coding an image on a coding unit block-by-block basis, the method comprising:

dividing a coding unit block included in the image into plural frequency transform blocks, and executing a frequency transform process on the coding unit block on a frequency transform block-by-block basis; and

executing a deblocking filtering process for eliminating coding distortion at a block boundary for each of the frequency transform blocks according to order in which the frequency transform process has been executed on the coding unit block.

19. An image coding method for coding an image on a coding unit block-by-block basis, the method comprising:

dividing a coding unit block included in the image into plural frequency transform blocks, and executing a frequency transform process on the coding unit block on a frequency transform block-by-block basis; and

coding the coding unit block on which the frequency transform process has been executed, and generating a coded stream in which luma information and chroma information of the image are collectively included for each of the frequency transform blocks.

20. An image processing method for performing plural first processes, by pipelining, on a coded stream obtained by dividing an image into plural coding unit blocks having at least two sizes and coding the image on a coding unit block-by-block basis, the image processing method comprising:

(a) performing, by the pipelining, the plural first processes on the coded stream by executing each of the plural first processes; and

(b) dividing or connect portions of the coded stream into plural first processing unit blocks each having a first size, and controlling step (a) to cause the plural first processes to be executed for each of the first processing unit blocks.

21. A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute the image processing method according to claim 20.

22. An integrated circuit for performing plural first processes, by pipelining, on a coded stream obtained by dividing an image into plural coding unit blocks having at least two sizes and coding the image on a coding unit block-by-block basis, the integrated circuit comprising:

plural first process units configured to perform, by the pipelining, the plural first processes on the coded stream by each executing one of the plural first processes; and

a control unit configured to divide or connect portions of the coded stream into plural first processing unit blocks each having a first size, and control the plural first process units to cause the plural first processes to be executed for each of the first processing unit blocks.