Optimisation of loops and data flow sections

• US 20130191817A1
• Filed: 12/28/2010
• Published: 07/25/2013
• Est. Priority Date: 12/28/2009
• Status: Active Grant

• Current Assignee: Hyperion Core, Inc.
• Original Assignee: Hyperion Core, Inc.
• Inventors: Vorbach, Martin
• Granted Patent: US 9,043,769 B2
• Time in Patent Office: Days
• US Class Current: 717/150
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: G06F 8/41 Compilation
• CPC Class Codes: G06F 8/4441 Reducing the execution time required by the program code
• CPC Class Codes: G06F 8/452 Loops
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Claims

1. A method for compiling code for a multi-core processor, comprising:

detecting and optimizing a loop,

partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism,

optimizing the loop iterations and/or loop counter for ideal mapping on hardware,

chaining the loop partitions

generating a list representing the execution sequence of the partitions.

2. A method for compiling code for a multi-core processor, comprising:

detecting and optimizing dataflow sections of the code,

partitioning the dataflow sections into partitions executable and mappable on physical hardware with optimal instruction level parallelism,

optimizing the outer control structure of the dataflow sections for ideal mapping on hardware,

chaining the dataflow partitions

generating a list representing the execution sequence of the partitions.

3. A method for operating a processor comprising:

scheduling by a first scheduler the available processing hardware resource,

providing a thread and/or microthread a list of respectively allocated hardware resources,

scheduling and mapping partitioned dataflow code onto the allocated hardware resources, and

configuring the interconnection between the hardware resources.