FinFET Body Contact and Method of Making Same

• US 20130193526A1
• Filed: 01/31/2012
• Published: 08/01/2013
• Est. Priority Date: 01/31/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lo, Ching-Hsiung, Lin, Wun-Jie, Tseng, Jen-Chou, Lee, Jam-Wem
• Granted Patent: US 8,735,993 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.

Claims

1. A semiconductor device comprising:

a substrate;

a fin raised above the substrate;

the fin comprising;

a first source/drain region in the fin;

a first body contact in the fin; and

a first portion of the fin, the first portion laterally between the first source/drain region and the first body contact.

2. The semiconductor device of claim 1, wherein the first portion comprises only fin material.

3. The semiconductor device of claim 1, wherein the fin contains dopants of a first conductivity type, the first source/drain region contains dopants of a second conductivity type, and the first body contact contains dopants of the first conductivity type.

4. The semiconductor device of claim 3, wherein the first conductivity type is p-type and the second conductivity type is n-type.

5. The semiconductor device of claim 1, wherein the fin further comprises a first gate structure over the fin, wherein the first gate structure is directly over the first portion of the fin.

6. The semiconductor device of claim 5, wherein the fin further comprises:

a second source/drain region in the fin, the second source/drain region laterally spaced from the first source drain region in a direction opposite of the first body contact; and

a second gate structure over the fin, wherein the second gate structure is laterally between the first source/drain region and the second source/drain region.

7. The semiconductor device of claim 6, wherein the fin further comprises:

a third source/drain region in the fin, the third source/drain region laterally spaced from the second source/drain region in a direction opposite the first source/drain region;

a third gate structure over the fin, wherein the third gate structure is laterally between the second source/drain region and the third source/drain region;

a second body contact in the fin;

a second portion of the fin, the second portion laterally between the third source/drain region and the second body contact; and

a fourth gate structure over the fin, wherein the fourth gate structure is directly over the second portion of the fin.

8. The semiconductor device of claim 7, wherein the fin further comprises:

a first isolation region in the fin, wherein the first isolation region is adjacent the first body contact on an opposite side from the first portion of the fin;

a fifth gate structure over the fin, wherein the fifth gate structure is partially located over the first body contact and partially over the first isolation region;

a second isolation region in the fin, wherein the second isolation region is adjacent the second body contact on an opposite side from the second portion of the fin; and

a sixth gate structure over the fin, wherein the sixth gate structure is partially located over the second body contact and partially over the second isolation region.

9. The semiconductor device of claim 8, wherein the first, fourth, fifth, and sixth gate structures are dummy gate structures.

10. A semiconductor device comprising:

a substrate;

a first semiconductor fin extending from the substrate, wherein the first semiconductor fin comprises;

a first source/drain region in the first semiconductor fin;

a second source/drain region in the first semiconductor fin;

a first gate structure on a top surface and sidewalls of the first semiconductor fin, wherein the first gate structure is laterally between the first source/drain region and the second source/drain region;

a first body contact in the first semiconductor fin; and

a second gate structure on a top surface and sidewalls of the first semiconductor fin, wherein the second gate structure is laterally between the first source/drain region and the first body contact.

11. The semiconductor device of claim 10, wherein the first semiconductor fin contains dopants of a first conductivity type, the first and second source/drain regions contain dopants of a second conductivity type, and the first body contact contains dopants of the first conductivity type.

12. The semiconductor device of claim 11, wherein the first conductivity type is p-type and the second conductivity type is n-type.

13. The semiconductor device of claim 10, wherein the first semiconductor fin further comprises:

a second body contact in the fin; and

a third gate structure on a top surface and sidewalls of the fin, wherein the third gate structure is laterally spaced between the second source/drain region and the second body contact.

14. The semiconductor device of claim 13, wherein the first semiconductor fin further comprises:

a first isolation region in the fin, wherein the first isolation region is adjacent the first body contact on an opposite side from the first source/drain region;

a fourth gate structure over the fin, wherein the fourth gate structure is partially located over the first body contact and partially over the first isolation region;

a second isolation region in the fin, wherein the second isolation region is adjacent the second body contact on an opposite side from the second source/drain region; and

a fifth gate structure over the fin, wherein the fifth gate structure is partially located over the second body contact and partially over the second isolation region.

15. The semiconductor device of claim 14, wherein the second, third, fourth, and fifth gate structures are dummy gate structures.

16. The semiconductor device of claim 15, wherein the semiconductor device further comprises:

a third body contact in the substrate, wherein the third body contact is laterally spaced from the first semiconductor fin and parallel to the first semiconductor fin; and

a third isolation region in the substrate, wherein the third isolation region is laterally between the first semiconductor fin the third body contact.

17. The semiconductor device of claim 16, wherein the semiconductor device further comprises:

a second semiconductor fin extending from the substrate, wherein the second semiconductor fin laterally spaced from the first semiconductor fin in a direction opposite from the third body contact, the second semiconductor fin being parallel to the first semiconductor fin, and the first, second, third, fourth, and fifth gate structures are on a top surface and sidewalls of the second semiconductor fin;

a third semiconductor fin extending from the substrate, wherein the third semiconductor fin laterally spaced from the second semiconductor fin in a direction opposite from the first semiconductor fin, the third semiconductor fin being parallel to the second semiconductor fin, and the first, second, third, fourth, and fifth gate structures are on a top surface and sidewalls of the third semiconductor fin;

a fourth semiconductor fin extending from the substrate, wherein the fourth semiconductor fin laterally spaced from the third semiconductor fin in a direction opposite from the second semiconductor fin, the fourth semiconductor fin being parallel to the third semiconductor fin, and the first, second, third, fourth, and fifth gate structures are on a top surface and sidewalls of the fourth semiconductor fin;

a fifth semiconductor fin extending from the substrate, wherein the fifth semiconductor fin laterally spaced from the fourth semiconductor fin in a direction opposite from the third semiconductor fin, the fifth semiconductor fin being parallel to the fourth semiconductor fin, and the first, second, third, fourth, and fifth gate structures are on a top surface and sidewalls of the fifth semiconductor fin;

a fourth body contact in the substrate, wherein the fourth body contact is laterally spaced from the fifth semiconductor fin and parallel to the fifth semiconductor fin; and

a fourth isolation region in the substrate, wherein the fourth isolation region is laterally between the fifth semiconductor fin the fourth body contact.

18. A method of forming a semiconductor structure, the method comprising:

forming a semiconductor fin on a substrate;

forming a first gate structure on a top surface and sidewalls of the semiconductor fin;

forming a second gate structure on a top surface and sidewalls of the semiconductor fin, wherein the second gate structure is laterally spaced from the first gate structure;

forming a third gate structure on a top surface and sidewalls of the semiconductor fin, wherein the third gate structure is laterally spaced form the first gate structure in a direction opposite from the second gate structure;

forming a first source/drain region in the semiconductor fin, wherein the first source/drain region is laterally between the first gate structure and the second gate structure;

forming a second source/drain region in the semiconductor fin, wherein the second source/drain region is laterally between the first gate structure and the third gate structure; and

forming a first body contact in the semiconductor fin, wherein the first body contact is laterally spaced from first source/drain region, and the second gate structure is laterally between the first source/drain region and the first body contact.

19. The method of claim 18, wherein the forming the first source/drain region comprises:

patterning the semiconductor fin to form a first recess; and

epitaxially growing the first source/drain region in the first recess.

20. The method of claim 18, wherein the forming the semiconductor structure further comprises:

forming a second body contact in the semiconductor fin, wherein the second body contact is laterally spaced from second source/drain region, and the third gate structure is laterally between the second source/drain region and the second body contact.