Transceiver Architecture and Methods for Demodulating and Transmitting Phase Shift Keying Signals

• US 20130195157A1
• Filed: 01/30/2013
• Published: 08/01/2013
• Est. Priority Date: 01/31/2012
• Status: Active Grant

• Current Assignee: Innophase, Inc.
• Original Assignee: Innophase, Inc.
• Inventors: Xu, Yang
• Granted Patent: US 8,917,759 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: H04L 27/2071 in which the data are represented by the carrier phase, e.g. systems with differential coding
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence

Abstract

A transceiver is described. The transceiver includes a first injection-locked oscillator and a second injection-locked oscillator. The transceiver also includes a first phase-locked loop coupled with the first injection-locked oscillator. The first phase-locked loop is configured to generate a first frequency reference. Further, the transceiver includes a second phase-locked loop coupled the second injection-locked oscillator. The second phase-locked loop is configured to generate a second frequency reference. The transceiver includes a mixer configured to receive the first phase-locked loop output and configured to receive said second injection-locked oscillator output. The mixer is also configured to generate a carrier frequency signal based on the first injection-locked oscillator output and the second injection-locked oscillator output. And, the transceiver includes a modulator configured to receive said carrier frequency signal.

Claims

1. A transceiver comprising:

a first injection-locked oscillator having a first input configured to receive a binary phase shift keying (“

BPSK”

) signal and a second input configured to receive a first frequency reference, said first injection-locked oscillator configured to generate a first injection-locked oscillator output;

a second injection-locked oscillator having a third input configured to receive said BPSK signal and a fourth input configured to receive a second frequency reference, said second injection-locked oscillator configured to generate a second injection-locked oscillator output;

a first phase-locked loop coupled with said second input of said first injection-locked oscillator, said first phase-locked loop configured to generate said first frequency reference;

a second phase-locked loop coupled with said fourth input of said second injection-locked oscillator, said second phase-locked loop configured to generate said second frequency reference;

a mixer configured to receive said first phase-locked loop output and configured to receive said second injection-locked oscillator output, said mixer configured to generate a carrier frequency signal based on said first injection-locked oscillator output and said second injection-locked oscillator output; and

a modulator configured to receive said carrier frequency signal.

2. The transceiver of claim 1 comprising:

a second mixer coupled with said first injection-locked oscillator and said second injection-locked oscillator.

3. The transceiver of claim 2 comprising:

a finite state machine coupled with said first phase-locked loop and coupled with said second phase-locked loop.

4. The transceiver of claim 3, wherein said finite state machine is coupled with said first phase-locked loop by a control signal.

5. The receiver of claim 4, wherein said control signal adjusts a divide factor of said first phase-locked loop.

6. The transceiver of claim 1, wherein said first phase-locked loop and said second phase-locked loop are a digital phase-locked loop.

7. The transceiver of claim 1, wherein said first phase-locked loop and said second phase-locked loop are an analog phase-locked loop.

8. The transceiver of claim 1 comprising:

a quadrature phase shift keying (“

QPSK”

) decomposition filter coupled with said first injection-locked oscillator and said second injection-locked oscillator.

9. The receiver of claim 1, wherein said first phase-locked loop is configured to receive a first output of said first injection-locked oscillator and said first reference frequency is based at least on said first output of said first injection-locked oscillator.

10. The receiver of claim 1, wherein said first frequency reference is greater than a carrier frequency of said BPSK signal and said second frequency reference is less than said carrier frequency of said BPSK signal.

11. A transceiver comprising:

a first injection-locked oscillator having a first input configured to receive a binary phase shift keying (“

BPSK”

) signal and a second input configured to receive a first frequency reference;

a second injection-locked oscillator having a third input configured to receive said BPSK signal and a fourth input configured to receive a second frequency reference;

a first injection-locked oscillator (“

ILO”

) control circuit coupled with said second input of said first injection-locked oscillator, said first injection-locked oscillator control circuit configured to generate said first frequency reference;

a second ILO control circuit coupled with said fourth input of said second injection-locked oscillator, said second injection-locked oscillator control circuit configured to generate said second frequency reference; and

a mixer configured to receive a first injection-locked oscillator output and configured to receive a second injection-locked oscillator output, said mixer configured to generate a carrier frequency signal based on said first injection-locked oscillator output and said second injection-locked oscillator output; and

a modulator configured to receive said carrier frequency signal.

12. The transceiver of claim 11 comprising:

a second mixer coupled with said first injection-locked oscillator and said second injection-locked oscillator.

13. The transceiver of claim 12 comprising:

a finite state machine coupled with said first ILO control circuit and coupled with said second ILO control circuit.

14. The transceiver of claim 13, wherein said control signal adjusts a tuning constant of said first injection-locked oscillator control circuit.

15. The transceiver of claim 11, wherein said modulator is a configured to receive a digital bit stream.

16. The transceiver of claim 11, wherein at least one of said first injection-locked oscillator control circuit and said second injection-locked oscillator control circuit is a phase-locked loop.

17. The transceiver of claim 11, wherein at least one of said first injection-locked oscillator control circuit and said second injection-locked oscillator control circuit is a frequency-locked loop.

18. The transceiver of claim 11, wherein said first phase-locked loop is configured to receive said first output of said first injection-locked oscillator and said first reference frequency is based at least on said first output of said first injection-locked oscillator.

19. The transceiver of claim 11, wherein said first frequency reference is greater than a carrier frequency of said BPSK signal and said second frequency reference is less than said carrier frequency of said BPSK signal.

20. A method for demodulating a signal and modulating a baseband signal comprising:

receiving a binary-phase shift keying signal;

generating a first channel based on said binary phase shift keyed signal;

generating a second channel based on said binary phase shift keyed signal;

processing said first channel using a first circuit including a first injection-locked oscillator coupled with a first injection-locked oscillator control circuit to generate a first output;

processing said second channel using a second circuit including a second injection-locked oscillator coupled with a second injection-locked oscillator control circuit to generate a second output;

multiplying said first output with said second output to generate a carrier frequency signal; and

modulating a baseband signal based on said carrier frequency signal.