SEMICONDUCTOR MEMORY DEVICE

• US 20130228839A1
• Filed: 03/01/2013
• Published: 09/05/2013
• Est. Priority Date: 03/05/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Arai, Yasuyuki
• Granted Patent: US 9,059,029 B2
• Time in Patent Office: Days
• US Class Current: 257/300
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor
• CPC Class Codes: H10B 12/377 having a storage electrode extension located over the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided.

Claims

1. A semiconductor memory device comprising:

a memory cell comprising;

a first transistor comprising;

a first semiconductor layer;

a first gate insulating layer over and in contact with the first semiconductor layer;

a first gate electrode which is in contact with the first gate insulating layer and overlaps with the first semiconductor layer; and

a source region and a drain region with a region of the first semiconductor layer overlapping with the first gate electrode located between the source region and the drain region;

a second transistor comprising;

a second semiconductor layer which overlaps with the first gate electrode and is electrically connected to the first gate electrode;

a second gate insulating layer in contact with a side surface of the second semiconductor layer; and

a second gate electrode which is in contact with the second gate insulating layer and at least partly covers the side surface of the second semiconductor layer; and

a capacitor comprising;

a capacitor layer in contact with a side surface of the first gate electrode; and

a first capacitor electrode which is in contact with the capacitor layer and at least partly covers the side surface of the first gate electrode.

2. The semiconductor memory device according to claim 1, wherein the second semiconductor layer comprises a semiconductor material having a wider band gap than silicon.

3. The semiconductor memory device according to claim 1, wherein the second semiconductor layer comprises an oxide semiconductor.

4. The semiconductor memory device according to claim 3, wherein the second semiconductor layer is in a non-single-crystal state.

5. The semiconductor memory device according to claim 3, wherein the second semiconductor layer comprises indium, tin, gallium, and zinc.

6. A semiconductor memory device comprising:

a memory cell comprising;

a first transistor comprising;

a first semiconductor layer;

a first gate insulating layer over and in contact with the first semiconductor layer;

a first gate electrode which is in contact with the first gate insulating layer and overlaps with the first semiconductor layer; and

a source region and a drain region with a region of the first semiconductor layer overlapping with the first gate electrode located between the source region and the drain region;

a second transistor comprising;

a second semiconductor layer which overlaps with the first gate electrode and is electrically connected to the first gate electrode;

a second gate insulating layer in contact with a side surface of the second semiconductor layer; and

a second gate electrode which is in contact with the second gate insulating layer and at least partly covers the side surface of the second semiconductor layer; and

a capacitor comprising;

a second capacitor electrode electrically connecting the first gate electrode to the second semiconductor layer;

a capacitor layer in contact with the second capacitor electrode; and

a first capacitor electrode which is in contact with the capacitor layer and at least partly covers a side surface of the second capacitor electrode.

7. The semiconductor memory device according to claim 6, wherein the second semiconductor layer comprises a semiconductor material having a wider band gap than silicon.

8. The semiconductor memory device according to claim 6, wherein the second semiconductor layer comprises an oxide semiconductor.

9. The semiconductor memory device according to claim 8, wherein the second semiconductor layer is in a non-single-crystal state.

10. The semiconductor memory device according to claim 8, wherein the second semiconductor layer comprises indium, tin, gallium, and zinc.