Non-Volatile Memory Systems and Methods

• US 20130235664A1
• Filed: 04/19/2013
• Published: 09/12/2013
• Est. Priority Date: 01/14/1999
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tran, Hieu Van, KHAN, Sakhawat M.
• Granted Patent: US 8,614,924 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Claims

1-87. -87. (canceled)

88. A method of programming a multilevel memory cell, the method comprising:

determine whether a margin of read said memory cell matches a certain criteria;

setting a program fail flag in the event the margin does not match said criteria;

perform binary search to determine data corresponding to content of read memory cell; and

allowing access to said memory cell.

127. The method of claim 88 further comprising:

processing upper program margin verify voltages; and

comparing the upper program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

128. The method of claim 88 further comprising:

processing lower program margin verify voltages; and

comparing the lower program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

129. The method of claim 88 further comprising entering an upper margin verify mode.

130. The method of claim 88 further comprising entering a lower margin verify mode.

131. The method of claim 88 further comprising autozeroing an input and output in order to zero out offset in an amplifier.

132. The method of claim 88 further comprising capacitively sensing an output of a memory cell via selective coupling of the reference sense amplifier to one or more reference memory subarrays.

133. The method of claim 88 further comprising selectively coupling the reference sense amplifier to a group of sense amplifiers to capacitively sense an output associated with the group of sense amplifiers.

134. The method of claim 88 further comprising:

coupling a reference array to reference memory subarrays; and

provide stored reference signals used for reading reference memory cells, the stored reference signals corresponding to detected reference signals.

89-126. -126. (canceled)

135. A system comprising:

one or more circuits configured for programming a multilevel memory cell, the one or more circuits configured to;

determine whether a read margin of said memory cell matches a certain criteria;

set a program fail flag in the event the margin does not match said criteria;

perform binary search to determine data corresponding to content of read memory cell; and

allow access to said memory cell.

136. The system of claim 135 wherein the system is configured to:

process upper program margin verify voltages; and

compare the upper program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

137. The system of claim 135 further configured to:

process lower program margin verify voltages; and

compare the lower program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.

138. The system of claim 135 wherein the system is configured to enter an upper margin verify mode.

139. The system of claim 135 wherein the system is configured to enter a lower margin verify mode.

140. The system of claim 135 wherein the system is configured to:

apply an erase algorithm programmed via fuses upon one selected erase block of memory cells at a time.

141. The system of claim 140 wherein erase blocks include a plurality of pages of memory cells.

142. The system of claim 140 wherein quantities of pages within the erase blocks are programmable via fuses for different user requirements and/or applications.

143. The system of claim 135 wherein the system is configured to:

apply a read algorithm programmed via fuses upon one selected page of memory cells at a time.

144. The system of claim 143 wherein quantities of memory cells within a page is programmable via fuses to optimize power consumption and/or data rate.

145. A method of reading and/or programming a multilevel memory cell, the method comprising:

determine whether a margin of said memory cell matches a certain criteria;

setting a program fail flag in the event the margin does not match said criteria;

perform binary search to determine data corresponding to content of read memory cell; and

allowing access to said memory cell.