HIGH POWER HIGH ISOLATION LOW CURRENT CMOS RF SWITCH

• US 20130252562A1
• Filed: 03/15/2013
• Published: 09/26/2013
• Est. Priority Date: 09/21/2010
• Status: Abandoned Application

• Current Assignee: DSP Group Ltd. (Synaptics Incorporated)
• Original Assignee: DSP Group Ltd. (Synaptics Incorporated)
• Inventors: Hasson, Yaron, Mostov, Alex
• Application Number:
  US13/836,698
• Publication Number:
  US 20130252562A1
• Time in Patent Office: Days
• US Class Current: 455/78
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

A novel and useful RF switch that comprises four transistors configured to have four operating states, wherein at any time at most one transistor is in ‘on’ state. The switch is an on-chip switch and is constructed in using CMOS processes and technology. The switch is optionally a double pole, double throw (DPDT) switch. The switch can be used in numerous mobile devices such as a cellular phone or in the handset or base station of a cordless phone. The switch optionally selects between two antennas and between transmitter and receiver circuits. Within the switch, at least one of the at least four transistors is optionally an N-channel Metal Oxide Semiconductor (NMOS) transistor. The switch can further comprise one or more logic control circuits providing biasing voltages to one or more of the transistors. Within the switch, the control circuit comprises logic components for providing appropriate biasing voltages to the drain, source and gate terminals of the transistors in the switch.

Claims

1. A radio frequency (RF) switch, comprising:

a first transistor operative to couple a transmit signal from a transmitter to a first antenna;

a second transistor operative to couple said transmit signal from a transmitter to a second antenna;

a third transistor operative to couple a receive signal from said first antenna to a receiver;

a fourth transistor operative to couple said receive signal from said second antenna to said receiver; and

a control circuit coupled to said first transistor, said second transistor, said third transistor and said fourth transistor, said control circuit operative to place only one of said four transistors in an on state while placing the remaining three transistors in a reverse biased off state.

2. The switch according to claim 1, wherein said first transistor, said second transistor, said third transistor and said fourth transistor comprise N channel Metal Oxide Semiconductor (NMOS) transistors.

3. The switch according to claim 1, further comprising a low pass filter (LPF) disposed between said control circuit and each of said first transistor, said second transistor, said third transistor and said fourth transistor, each LPF operative to suppress RF leakage from a drain, gate and source of each transistor to said logic control circuit thereby reducing RF signal loss.

4. The switch according to claim 1, wherein said four transistors are configured as a double pole, double throw switch.

5. A radio frequency (RF) switch, comprising:

a first transistor having a source, drain and gate, said first transistor operative to couple a transmit signal from a transmitter to a first antenna;

a second transistor having a source, drain and gate, said second transistor operative to couple said transmit signal from a transmitter to a second antenna;

a third transistor having a source, drain and gate, said third transistor operative to couple a receive signal from said first antenna to a receiver;

a fourth transistor having a source, drain and gate, said fourth transistor operative to couple said receive signal from said second antenna to said receiver;

a control circuit coupled to the source, drain and gate terminals of said first transistor, said second transistor, said third transistor and said fourth transistor, said control circuit operative to generate source, drain and gate signals such that only one of said four transistors is in an on state while placing the remaining three transistors in a reverse bias off state.

6. The switch according to claim 5, wherein said first transistor, said second transistor, said third transistor and said fourth transistor comprise N channel Metal Oxide Semiconductor (NMOS) transistors.

7. The switch according to claim 5, further comprising a low pass filter (LPF) disposed between said control circuit and the source, drain and gate of each of said first transistor, said second transistor, said third transistor and said fourth transistor, each LPF operative to suppress RF leakage from said drain, gate and source of each transistor to said logic control circuit thereby reducing RF signal loss.

8. The switch according to claim 7, wherein said LPF comprises an RC network.

9. The switch according to claim 5, wherein one of said four transistors is placed in said on state by applying a high voltage applied to its gate while its source and drain are both coupled to ground.

10. The switch according to claim 5, wherein said remaining transistors are placed in said reverse biased off state by applying a high voltage to their drain and source while their gate is coupled to ground.

11. The switch according to claim 5, wherein said four transistors are configured as a double pole, double throw switch.

12. The switch according to claim 5, further comprising dc blocking capacitors coupled to the drain and source of each said transistor, said dc blocking capacitors operative to allow the biasing of each transistor independently of the respective three neighboring transistors.

13. The switch according to claim 5, further comprising package bond wires connecting transmitter, receiver, first antenna and second antenna internal die pads to external switch package pins, said bin wires operative to form a matching network when combined with external shunt capacitors connected thereto.

14. A method for use with a radio frequency switch, said method comprising:

providing a first transistor having a source, drain and gate, said first transistor operative to couple a transmit signal from a transmitter to a first antenna;

providing a second transistor having a source, drain and gate, said second transistor operative to couple said transmit signal from a transmitter to a second antenna;

providing a third transistor having a source, drain and gate, said third transistor operative to couple a receive signal from said first antenna to a receiver;

providing a fourth transistor having a source, drain and gate, said fourth transistor operative to couple said receive signal from said second antenna to said receiver;

generating source, drain and gate signals for said first transistor, said second transistor, said third transistor and said fourth transistor, such that only one of said four transistors is in an on state while the remaining three transistors are in a reverse bias off state;

wherein a transistor is placed in an on state by forward biasing its gate-source junction; and

wherein a transistor is placed in an off state by reverse biasing its gate-source junction.

15. The method according to claim 14, wherein said first transistor, said second transistor, said third transistor and said fourth transistor comprise N channel Metal Oxide Semiconductor (NMOS) transistors.

16. The method according to claim 14, further comprising providing a low pass filter (LPF) disposed between said control circuit and the source, drain and gate of each of said first transistor, said second transistor, said third transistor and said fourth transistor.

21. The device according to claim 15, wherein said four transistors are configured as a double pole, double throw switch.

17. A wireless communication device, comprising:

a first antenna;

a second antenna;

a transmitter;

a receiver;

an RF switch;

said RF switch comprising;

a first transistor operative to couple a transmit signal from said transmitter to said first antenna;

a second transistor operative to couple said transmit signal from a transmitter to said second antenna;

a third transistor operative to couple a receive signal from said first antenna to said receiver;

a fourth transistor operative to couple said receive signal from said second antenna to said receiver; and

a control circuit coupled to said first transistor, said second transistor, said third transistor and said fourth transistor, said control circuit operative to place only one of said four transistors in an on state while placing the remaining three transistors in a reverse biased off state.

18. The device according to claim 17, wherein said first transistor, said second transistor, said third transistor and said fourth transistor comprise N channel Metal Oxide Semiconductor (NMOS) transistors.

19. The device according to claim 17, further comprising a low pass filter (LPF) disposed between said control circuit and each of said first transistor, said second transistor, said third transistor and said fourth transistor, each LPF operative to suppress RF leakage from a drain, gate and source of each transistor to said logic control circuit thereby reducing RF signal loss.

20. The device according to claim 17, wherein said LPF comprises an RC network.