SEMICONDUCTOR DEVICE

• US 20130256771A1
• Filed: 05/23/2013
• Published: 10/03/2013
• Est. Priority Date: 12/28/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi, Nagatsuka, Shuhei, Matsuzaki, Takanori, Inoue, Hiroki
• Granted Patent: US 9,153,589 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

Claims

1. (canceled)

2. A semiconductor device comprising:

a first transistor comprising a gate electrode;

a first insulating layer comprising an opening, wherein the gate electrode of the first transistor is positioned in the opening;

a second transistor comprising;

an oxide semiconductor layer on the first insulating layer;

a first conductive layer and a second conductive layer over the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer; and

a gate electrode over the second insulating layer and overlapping with the oxide semiconductor layer

a switching element electrically connected the second conductive layer; and

a driver circuit electrically connected to the second conductive layer through the switching element,

wherein the oxide semiconductor layer comprises indium and zinc,

wherein the first conductive layer is in contact with the surface of the gate electrode of the first transistor and the first insulating layer.

3. The semiconductor device according to claim 2, wherein the oxide semiconductor layer further comprises gallium.

4. The semiconductor device according to claim 2, wherein the first insulating layer is a silicon oxide film or a silicon oxynitride film.

5. The semiconductor device according to claim 2, wherein the surface of the first insulating layer and the surface of the gate electrode of the first transistor are planarized by a chemical mechanical polishing.

6. The semiconductor device according to claim 2, wherein the first conductive layer and the second conductive layer are each in contact with the oxide semiconductor layer.

7. The semiconductor device according to claim 2, wherein the gate electrode of the second transistor overlaps with the first conductive layer and the second conductive layer.

8. The semiconductor device according to claim 2, further comprising a third conductive layer over the second insulating layer, wherein the third conductive layer overlaps with the first conductive layer.

9. The semiconductor device according to claim 2, wherein a channel formation region of the first transistor comprises a semiconductor material other than an oxide semiconductor material.

10. The semiconductor device according to claim 2, wherein a channel formation region of the first transistor comprises silicon.

11. The semiconductor device according to claim 2, wherein a channel formation region of the first transistor is located in a semiconductor substrate.

12. The semiconductor device according to claim 2, wherein the oxide semiconductor layer comprises hydrogen in a concentration of 5×

10¹⁹ atoms/cm³ or less.

13. A semiconductor device comprising:

a first transistor comprising a gate electrode;

a first insulating layer surrounding the gate electrode of the first transistor;

a second transistor comprising;

an oxide semiconductor layer on the first insulating layer;

a first conductive layer and a second conductive layer over the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer; and

a gate electrode over the second insulating layer and overlapping with the oxide semiconductor layer;

a switching element electrically connected the second conductive layer; and

a driver circuit electrically connected to the second conductive layer through the switching element,

wherein the oxide semiconductor layer comprise indium and zinc,

wherein a surface of the gate electrode of the first transistor and a surface of the first insulating layer are included in a same planarized surface, and

wherein the first conductive layer is in contact with the surface of the gate electrode of the first transistor.

14. The semiconductor device according to claim 13, wherein the oxide semiconductor layer further comprises gallium.

15. The semiconductor device according to claim 13, wherein the first insulating layer is a silicon oxide film or a silicon oxynitride film.

16. The semiconductor device according to claim 13, wherein the surface of the first insulating layer and the surface of the gate electrode of the first transistor are planarized by a chemical mechanical polishing.

17. The semiconductor device according to claim 13, wherein the first conductive layer and the second conductive layer are each in contact with the oxide semiconductor layer.

18. The semiconductor device according to claim 13, wherein the gate electrode of the second transistor overlaps with the first conductive layer and the second conductive layer.

19. The semiconductor device according to claim 13, further comprising a third conductive layer over the second insulating layer, wherein the third conductive layer overlaps with the first conductive layer.

20. The semiconductor device according to claim 13, wherein a channel formation region of the first transistor comprises a semiconductor material other than an oxide semiconductor material.

21. The semiconductor device according to claim 13, wherein a channel formation region of the first transistor comprises silicon.

22. The semiconductor device according to claim 13, wherein a channel formation region of the first transistor is located in a semiconductor substrate.

23. The semiconductor device according to claim 13, wherein the oxide semiconductor layer comprises hydrogen in a concentration of 5×

10¹⁹ atoms/cm³ or less.

24. A semiconductor device comprising:

a first transistor comprising a gate electrode;

a first insulating layer over the first transistor, wherein the gate electrode of the first transistor is exposed from the first insulating layer;

a second transistor comprising;

an oxide semiconductor layer on the first insulating layer;

a first conductive layer and a second conductive layer over the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer; and

a gate electrode over the second insulating layer and overlapping with the oxide semiconductor layer;

a switching element electrically connected the second conductive layer; and

a driver circuit electrically connected to the second conductive layer through the switching element,

wherein the oxide semiconductor layer comprises indium and zinc,

wherein the first conductive layer is in contact with the surface of the gate electrode of the first transistor and the first insulating layer.

25. The semiconductor device according to claim 24, wherein the oxide semiconductor layer further comprises gallium.

26. The semiconductor device according to claim 24, wherein the first insulating layer is a silicon oxide film or a silicon oxynitride film.

27. The semiconductor device according to claim 24, wherein the surface of the first insulating layer and the surface of the gate electrode of the first transistor are planarized by a chemical mechanical polishing.

28. The semiconductor device according to claim 24, wherein the first conductive layer and the second conductive layer are each in contact with the oxide semiconductor layer.

29. The semiconductor device according to claim 24, wherein the gate electrode of the second transistor overlaps with the first conductive layer and the second conductive layer.

30. The semiconductor device according to claim 24, further comprising a third conductive layer over the second insulating layer, wherein the third conductive layer overlaps with the first conductive layer.

31. The semiconductor device according to claim 24, wherein a channel formation region of the first transistor comprises a semiconductor material other than an oxide semiconductor material.

32. The semiconductor device according to claim 24, wherein a channel formation region of the first transistor comprises silicon.

33. The semiconductor device according to claim 24, wherein a channel formation region of the first transistor is located in a semiconductor substrate.

34. The semiconductor device according to claim 24, wherein the oxide semiconductor layer comprises hydrogen in a concentration of 5×

10¹⁹ atoms/cm³ or less.