BUILT-IN SELF-TEST METHOD AND STRUCTURE

• US 20130265068A1
• Filed: 04/10/2012
• Published: 10/10/2013
• Est. Priority Date: 04/10/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Amoah, Yoba, Ellis-Monaghan, John J., Kuo, Roger C., Leitch, Molly J., Zhang, Zhihong
• Granted Patent: US 8,890,557 B2
• Time in Patent Office: Days
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G11C 2029/1206 Location of test circuitry on chip or wafer
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Abstract

A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST.

Claims

1. A method of testing a semiconductor wafer, the method comprising:

placing a probe on a first chip on the semiconductor wafer;

testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault;

progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault;

moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and

testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribe line ABIST does not indicate a fault in the subsequent scribe line ABIST.

2. The method of claim 1, further comprising moving the probe point to the further subsequent chip and retesting the further subsequent scribe line ABIST in response to determining the ABIST for the further subsequent chip indicates the fault in the ABIST for the subsequent chip.

3. The method of claim 1, wherein the testing includes contacting a probe point with a testing probe.

4. The method of claim 1, wherein the probe point remains fixed until the fault is indicated.

5. The method of claim 1, wherein each the subsequent chip is adjacent to the first chip, and the further subsequent chip is adjacent to the subsequent chip.

6. The method of claim 1, further comprising repeating the moving of the probe point and the testing of the further subsequent scribe line ABIST for a remainder of chips on the semiconductor wafer.

7. The method of claim 6, further comprising performing a functional test on the semiconductor wafer after the repeating of the moving of the probe point and the testing of the further subsequent scribe line ABIST for the remainder of the chips on the semiconductor wafer.

8. The method of claim 1, wherein the scribe line ABIST for the first chip, the subsequent chip and the further subsequent chip are electrically connected.

9. The method of claim 1, wherein the scribe line ABIST for the first chip, the subsequent chip and the further subsequent chip each include circuitry for providing an identity when probed.

10. The method of claim 1, wherein the scribe line ABIST for the first chip, the subsequent chip and the further subsequent chip are each digitally testable.

11. A semiconductor wafer structure, comprising:

a plurality of chips; and

a plurality of scribe lines, each scribe line separating two adjacent chips in the plurality of chips,

wherein each scribe line includes a built-in self-test (BIST) engine configured to provide identity information about the scribe line in response to contact from a probe.

12. The semiconductor wafer structure of claim 11, the BIST engine further including a digitally testable probe point.

13. The semiconductor wafer structure of claim 11, wherein adjacent scribe lines in the plurality of scribe lines are electrically connected.

14. The semiconductor wafer structure of claim 13, wherein the contact from the probe on a first scribe line allows for testing of the plurality of scribe lines without moving the probe point.

15. The semiconductor wafer structure of claim 13, further comprising a transmission gate between at least two of the plurality of scribe lines, the transmission gate enabling the adjacent scribe lines to be electrically disconnected.

16. A method of testing a semiconductor wafer, the method comprising:

placing a probe on a chip on the semiconductor wafer;

testing a scribe line automatic built-in self-test (ABIST) for the chip to search for a fault;

progressively testing a subsequent scribe line ABIST for each of a plurality of subsequent chips on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault;

moving the probe point to a first subsequent chip and retesting the subsequent scribe line ABIST for the first subsequent chip in response to determining the ABIST for the first subsequent chip indicates a fault;

moving the probe point to a further subsequent chip in the plurality of subsequent chips and testing a further subsequent scribe line ABIST for the further subsequent chip in response to the retesting of the subsequent scribe line ABIST indicating a fault; and

testing a remainder of the plurality of subsequent chips to search for an additional fault.

17. The method of claim 16, wherein the testing includes contacting a probe point on the chip with a testing probe.

18. The method of claim 16, wherein the scribe line ABIST for the chip, the subsequent chip and the further subsequent chip are electrically connected.

19. The method of claim 16, wherein the scribe line ABIST for the chip, the subsequent chip and the further subsequent chip each include circuitry for providing an identity when probed.

20. The method of claim 16, wherein the scribe line ABIST for the chip, the subsequent chip and the further subsequent chip are each digitally testable.