RC Corner Solutions for Double Patterning Technology

• US 20130275927A1
• Filed: 05/23/2012
• Published: 10/17/2013
• Est. Priority Date: 04/13/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, Ke-Ying, Chao, Hsiao-Shu, Cheng, Yi-Kan
• Granted Patent: US 8,751,975 B2
• Time in Patent Office: Days
• US Class Current: 716/53
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.

Claims

1. A method comprising:

determining model parameters for forming an integrated circuit; and

generating a techfile using the model parameters, wherein the techfile comprises at least two of a C_worst table, a C_best table, and a C_nominal table, and wherein;

the C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other;

the C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other; and

the C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other, wherein the techfile is embodied on a tangible non-transitory storage medium.

2. The method of claim 1, wherein the step of generating the techfile is performed using a computer.

3. The method of claim 1, wherein the step of generating the techfile comprises:

determining a maximum shift of a first lithography mask relative to a second lithography mask, wherein the first and the second lithography masks are comprised in a double patterning mask set;

selecting a shift magnitude smaller than the maximum shift, wherein the shift magnitude represents a shift of a first net in the first lithography mask relative to second nets in the second lithography mask;

calculating coupling capacitance values between the first net and each of the second nets;

calculating a total capacitance of the capacitance values;

repeating the steps of selecting, calculating the coupling capacitance values, and calculating the total capacitance, wherein in each cycle of the repeating, an additional shift magnitude different from the shift magnitude is selected, and an additional total parasitic capacitance is calculated;

selecting a greatest capacitance from the total parasitic capacitance and the additional total parasitic capacitance; and

selecting a smallest capacitance from the total parasitic capacitance and the additional total parasitic capacitance.

4. The method of claim 3 further comprising converting the greatest capacitance and the smallest capacitance into an equivalent k_worst value and a k_best value, respectively, wherein the k_worst value represents a k value that causes a parasitic capacitance between the first net and one of the second nets to increase to the greatest capacitance when the first lithography mask shift relative to the second lithography mask, and wherein the k_best value represents a k value that causes a parasitic capacitance between the first net and one of the second nets to reduce to the smallest capacitance when the first lithography mask shift relative to the second lithography mask.

5. The method of claim 4 further comprising forming a k_worst table and a k_best table, wherein the k_worst table stores k_worst values of nets as a function of different spacings and different widths, and wherein the k_best table stores k_best values of the nets as a function of the different spacings and the different widths.

6. The method of claim 5 further comprising calculating the C_worst table and the C_best table from the k_worst table and the k_best table, respectively.

7. The method of claim 1 further comprising calculating the C_nominal table from a k_nominal value.

8. A method comprising:

analyzing polygons in a layout of an integrated circuit, wherein the layout is embodied on a tangible non-transitory computer-readable medium;

partitioning the polygons into nets; and

finding at least one parasitic capacitance of each of the nets from a techfile, wherein the techfile comprises at least two of a C_worst table, a C_best table, and a C_nominal table, and wherein;

the C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other;

the C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other; and

the C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other, wherein during the step of finding, a width and a spacing of the each of the nets are used to index into at least one of the C_worst table, the C_best table, and the C_nominal table.

9. The method of claim 8, wherein the step of finding at least one parasitic capacitance comprises, for at least one of the each of the nets, finding a C_worst value form the C_worst table, finding a C_best value form the C_best table, and finding a C_nominal value form the C_nominal table.

10. The method of claim 9, wherein the step of finding at least one parasitic capacitance comprises, for each of the nets, finding a C_worst value from the C_worst table, finding a C_best value from the C_best table, and finding a C_nominal value from the C_nominal table.

11. The method of claim 9 further comprising:

pre-determining a global process corner; and

identifying one of the C_worst table, the C_best table, and the C_nominal table as a default table corresponding to the global process corner, wherein in the step of finding at least one parasitic capacitance of each of the nets from the techfile, the at least one parasitic capacitance is found from the default table.

12. The method of claim 11 further comprising, in response to a pre-marking of selected nets in the nets of the polygons as corresponding to a process corner different from the global process corner, finding capacitance values of the selected nets from one of the C_worst table, the C_best table, and the C_nominal table different from the default table.

13. The method of claim 9 further comprising:

reading mask designators of the nets from the layout; and

for portions of the nets (same-mask nets) that are marked with the same one of the mask designators, replacing parasitic capacitance values of the same-mask nets with nominal capacitances found from the C_nominal table.

14. The method of claim 9 further comprising writing the at least one parasitic capacitance of each of the nets into netlists, wherein the netlists are embodied on a tangible non-transitory computer-readable medium.

15. The method of claim 14 further comprising:

retrieving the at least one parasitic capacitance from the netlists; and

simulating a best performance, a nominal performance, and a worst performance of the integrated circuit.

16. A method comprising:

analyzing polygons in a layout of an integrated circuit, wherein the layout is embodied on a tangible non-transitory computer-readable medium;

partitioning the polygons into nets; and

finding at least two of a worst capacitance, a best capacitance, and a nominal capacitance for each of the nets from a C_worst table, a C_best table, and a C_nominal table, respectively, wherein the step of finding comprises indexing into the C_worst table, the C_best table, and the C_nominal table using widths and spacings of the nets as indexes.

17. The method of claim 16 further comprising:

reading colors of the nets from the layout; and

replacing parasitic capacitance values of portions of the nets that have a same color with nominal capacitances found from the C_nominal table.

18. The method of claim 16 further comprising writing the at least two of the worst capacitance, the best capacitance, and the nominal capacitance into netlists, wherein the worst capacitance, the best capacitance, and the nominal capacitance are associated with the each of the nets, and wherein the netlists are embodied on an additional tangible non-transitory computer-readable medium.

19. The method of claim 18 further comprising:

retrieving the worst capacitance, the best capacitance, and the nominal capacitance from the netlists; and

simulating a worst performance, a best performance, and a nominal performance of the integrated circuit using the worst capacitance, the best capacitance, and the nominal capacitance, respectively.

20. The method of claim 16, wherein:

the C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other;

the C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other; and

the C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other, wherein the techfile is embodied on a tangible non-transitory storage medium.