CARBON NANOTUBE FIELD EMISSION DEVICE WITH OVERHANGING GATE

• US 20130280830A1
• Filed: 06/17/2013
• Published: 10/24/2013
• Est. Priority Date: 06/18/2007
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: TODA, Risaku, BRONIKOWSKI, Michael J., LUONG, Edward M., MANOHARA, Harish
• Granted Patent: US 8,916,394 B2
• Time in Patent Office: Days
• US Class Current: 438/20
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01J 1/3042 microengineered, e.g. Spindt-type
• CPC Class Codes: H01J 1/3044 Point emitters
• CPC Class Codes: H01J 2203/0224 Arrangement of gate openings
• CPC Class Codes: H01J 3/021 Electron guns using a field emission, photo emission, or secondary emission electron source
• CPC Class Codes: H01J 3/022 with microengineered cathode, e.g. Spindt-type
• CPC Class Codes: H01J 9/025 of field emission cathodes
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: Y10S 977/842 for carbon nanotubes or fullerenes
• CPC Class Codes: Y10S 977/939 Electron emitter, e.g. spindt emitter tip coated with nanoparticles

Abstract

A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.

Claims

1-4. -4. (canceled)

5. A semiconductor process applied to a wafer, the wafer comprising a silicon substrate;

a first insulator layer on the silicon substrate;

a first silicon layer on the first insulator layer;

a second insulator layer on the first silicon layer; and

a second silicon layer on the second insulator layer;

the semiconductor process comprising;

etching through the second silicon layer, through the second insulator layer, and through the first silicon layer to the first insulator layer to define a hole;

lateral etching in the first silicon layer to laterally enlarge the hole at the first silicon layer;

etching through the first insulator layer to the substrate, so that the hole has a bottom that includes the substrate;

depositing a removable material on the wafer;

forming an array of carbon nanotubes at the bottom of the hole on the substrate; and

removing the removable material from the wafer after forming the array of carbon nanotubes.

6. The semiconductor process as set forth in claim 5, where the depositing the removable material on the wafer comprises depositing the removable material on the substrate at the bottom of the hole.

7. The semiconductor process as set forth in claim 6, where forming the array of carbon nanotubes at the bottom of the hole on the substrate further comprises:

patterning the photoresist material to provide a pattern for a catalyst;

depositing the catalyst on the substrate at the bottom of the hole; and

growing the array of carbon nanotubes on the catalyst.

8. The semiconductor process as set forth in claim 5, where depositing the removable material comprises depositing the removable material on the wafer so that the removable material bridges the opening of the hole.

9. The semiconductor process as set forth in claim 8, where forming the array of carbon nanotubes at the bottom of the hole on the substrate further comprises:

patterning the removable material to provide a pattern for a catalyst;

depositing the catalyst on the substrate at the bottom of the hole; and

growing the array of carbon nanotubes on the catalyst.

10. The semiconductor process as set forth in claim 5, where the removable material is a photoresist material.

11. The semiconductor process as set forth in claim 5, further comprising depositing a second material on the wafer after removing the removable material from the wafer.

12. The semiconductor process as set forth in claim 11, where the second material comprises sol-gel material or micro glass-blowing material.

13. The semiconductor process as set forth in claim 12, where the micro glass-blowing material is a sol-gel or epoxy material.

14. The semiconductor process as set forth in claim 9, where patterning the removable material to provide a pattern for a catalyst comprises forming a plurality of openings through which the catalyst for carbon nanotube formation is adapted to be deposited onto the bottom of the hole on the substrate.

15. The semiconductor process as set forth in claim 9, where the catalyst is comprised within a catalyst dot array.

16. The semiconductor process as set forth in claim 5, where the first and second insulator layers comprise silicon dioxide.

17. The semiconductor process as set forth in claim 5, where the second silicon layer forms a gate with respect to at least one carbon nanotubes in the array of carbon nanotubes at the bottom of the hole on the substrate.

18. The semiconductor process as set forth in claim 5, where the hole has a top and a sidewall, the second silicon layer forming at least a portion of the sidewall wherein the second silicon layer at the top of the hole overhangs the sidewall.