SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF
First Claim
1. A semiconductor device comprising:
- a plurality of memory elements being in a matrix, each memory element including;
a plurality of transistors;
a capacitor; and
a data storage portion configured to store data for an error detection,wherein the data storage portion includes one of a source and a drain of first one of the plurality of transistors, a gate of second one of the plurality of transistors, and a first electrode of the capacitor, andwherein the first one of the plurality of transistors comprises an oxide semiconductor layer.
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Accused Products
Abstract
An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error.
36 Citations
18 Claims
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1. A semiconductor device comprising:
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a plurality of memory elements being in a matrix, each memory element including; a plurality of transistors; a capacitor; and a data storage portion configured to store data for an error detection, wherein the data storage portion includes one of a source and a drain of first one of the plurality of transistors, a gate of second one of the plurality of transistors, and a first electrode of the capacitor, and wherein the first one of the plurality of transistors comprises an oxide semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for driving a semiconductor device comprising the steps of:
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calculating a remainder; storing the remainder in a cyclic redundancy check memory; detecting an error of an i-th row with use of the remainder by a cyclic redundancy check; performing processing of an i+1-th row if there is no error in the i-th row; writing data to be input to the i-th row which is stored in a configuration memory if there is an error in the i-th row; and repeating the step of detecting an error and the step of writing data until no error is detected, wherein the cyclic redundancy check memory has a lower error rate than the configuration memory. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A readable memory device storing a computer program for detecting an error in a memory of a semiconductor device, when the computer program is executed in the semiconductor device or a processor, the semiconductor device or the processor conducting the steps of:
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calculating a remainder; storing the remainder in a cyclic redundancy check memory; detecting an error of an i-th row with use of the remainder by a cyclic redundancy check; performing processing of an i+1-th row when there is no error in the i-th row; writing data to be input to the i-th row which is stored in a configuration memory when there is an error in the i-th row; and repeating the step of detecting an error and the step of writing data until no error is detected, wherein the cyclic redundancy check memory has a lower error rate than the configuration memory. - View Dependent Claims (15, 16, 17, 18)
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Specification