STORING CACHE METADATA SEPARATELY FROM INTEGRATED CIRCUIT CONTAINING CACHE CONTROLLER

• US 20130290607A1
• Filed: 04/30/2012
• Published: 10/31/2013
• Est. Priority Date: 04/30/2012
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Chang, Jichuan, Ranganathan, Parthasarathy, Meza, Justin James
• Granted Patent: US 10,474,584 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 3/0667 at data level, e.g. file, record or object virtualisation
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A technique includes using a cache controller of an integrated circuit to control a cache including cached data content and associated cache metadata. The technique includes storing the metadata and the cached data content off of the integrated circuit and organizing the storage of the metadata relative to the cached data content such that a bus operation initiated by the cache controller to target the cached data content also targets the associated metadata.

Claims

1. A method comprising:

using a cache controller to control a cache comprising cached data content and associated cache metadata;

storing the cache metadata separately from an integrated circuit that contains the cache controller; and

organizing the storage of the metadata relative to the cached data content such that a memory bus operation initiated by the cache controller to target the cached data content also targets the associated metadata.

2. The method of claim 1, wherein the organizing comprises:

embedding the associated metadata in error code correction data associated with the cached data content.

3. The method of claim 1, wherein memory bus operation comprises a memory bus operation targeting a row of a memory and the organizing comprises storing the metadata and the cached data in the same row of the memory.

4. The method of claim 3, wherein the cached data comprises a plurality blocks of cached data, and the metadata comprises metadata for the blocks.

5. The method of claim 1, wherein the cached data content and the metadata are stored in a volatile memory, the method further comprises using the cache controller to control the cache in response to accesses to data stored in a non-volatile memory.

6. The method of claim 1, further comprising:

providing a metadata cache store on the integrated circuit to cache the metadata.

7. The method of claim 1, wherein the using comprises organizing the cache to employ direct mapping or set-associative schemes among data blocks and the cached content.

8. An apparatus comprising:

a primary data store comprising non-volatile memory;

a cache data store for the primary data store comprising volatile memory, the cache data store comprising cached data content and cache metadata associated with the cached data;

a memory bus coupled to the primary data store and the cache data store; and

a cache controller of an integrated circuit separate from the cache data store to initiate a bus operation on the memory bus to concurrently target the cached data content and the associated metadata.

9. The apparatus of claim 8, wherein the bus operation comprises a read operation or a write operation.

10. The apparatus of claim 8, wherein the bus operation comprises a burst operation to access a row of the volatile memory.

11. The apparatus of claim 8, wherein the metadata associated with the cached data is embedded in error code correction data associated with the cached data content.

12. The apparatus of claim 8, wherein the cache data store comprises a data row formed from a plurality blocks of the cached data and a block containing the associated metadata for the blocks of the cached data.

13. The apparatus of claim 8, wherein the controller is adapted to determine whether a cache hit occurs for the cache data store in response to a request targeting the primary data store.

14. The apparatus of claim 13, wherein the cache controller further comprises another cache store, and the memory controller is adapted to use the another cache to determine whether an associated cache content block is stored in the cache store that includes the volatile memory in response to the cache hit.

15. The apparatus of claim 14, wherein the cache controller is adapted to selectively access the associated metadata in response to a cache miss occurring for the another cache.

16. An apparatus comprising:

an integrated circuit comprising a cache controller, a buffer to store a pending memory access request and a first cache to store cached metadata associated with cache metadata stored in a second cache external to the integrated circuit,

wherein the cache controller is adapted to, in response to the request, determine whether a cache miss occurs for the first cache and based on the determination, selectively speculatively fetch data from a primary data store external to the integrated circuit.

17. The apparatus of claim 16, wherein the cache controller is further adapted to estimate a speculation accuracy and base the speculative prefetch based at least in part on the estimated speculation accuracy.

18. The apparatus of claim 16, wherein the metadata comprises a cache tag address.

19. The apparatus of claim 16, wherein the integrated circuit further comprises a victim cache to store data evicted from the second cache.

20. The apparatus of claim 16, wherein the cache controller is adapted to perform the speculative prefetch based at least in part on a confidence prediction outcome.