TRENCH SEMICONDUCTOR DEVICES WITH EDGE TERMINATION STRUCTURES, AND METHODS OF MANUFACTURE THEREOF

• US 20130307060A1
• Filed: 09/12/2012
• Published: 11/21/2013
• Est. Priority Date: 05/17/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chen, Jingjing, WANG, PEILIN, De Fresart, Edouard D.
• Granted Patent: US 9,368,576 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Claims

1. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region;

forming a gate structure in a first trench in the active region of the semiconductor substrate, wherein the gate structure has a first side and a second side;

forming a termination structure in a second trench in the edge region of the semiconductor substrate, wherein the termination structure has an active region facing side and a device perimeter facing side;

forming first and second source regions of a first conductivity type in the semiconductor substrate adjacent both the first side and the second side of the gate structure; and

forming a third source region in the semiconductor substrate adjacent the active region facing side of the termination structure.

2. The method of claim 1, wherein providing the semiconductor substrate comprises:

providing a first semiconductor layer having the first conductivity type and defining the bottom surface, wherein the first semiconductor layer corresponds to a drain of the device; and

epitaxially forming a second semiconductor layer having the first conductivity type over the first semiconductor layer and defining the top surface, wherein the first and second trenches extend from the top surface into but not through the second semiconductor layer, and portions of the second semiconductor layer underlying the gate structure and the termination structure correspond to drift spaces of the device.

3. The method of claim 1, further comprising:

forming a gate feed structure above the top surface in the edge region in contact with the termination structure and extending over the device perimeter facing side of the termination structure toward a perimeter of the device.

4. The method of claim 1, wherein the termination structure substantially surrounds the active region.

5. The method of claim 4, further comprising:

forming an extension electrode in a third trench in the edge region, wherein the extension electrode extends from the device perimeter facing side of the termination structure; and

forming a gate feed structure above the top surface in the edge region in contact with an end of the extension electrode and extending toward a perimeter of the device.

6. The method of claim 1, further comprising:

forming a body region of a second conductivity type in the semiconductor substrate between the gate structure and the termination structure, wherein the body region extends from the first side of the gate structure to the active region facing side of the termination structure, and wherein the first and third source regions are formed in the body region.

7. The method of claim 6, further comprising:

forming an enhanced body region of the second conductivity type and a higher doping density in the body region.

8. The method of claim 1, further comprising:

forming at least one additional gate structure in at least one additional trench in parallel with the first trench; and

forming additional source regions in the semiconductor substrate adjacent both sides of the at least one additional gate structure.

9. A method for forming a trench metal oxide semiconductor device, comprising:

providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region;

forming a plurality of parallel gate structures in a plurality of parallel first trenches in the active region of the semiconductor substrate, wherein each of the gate structures has a first side and a second side;

forming a termination structure in a second trench in the edge region of the semiconductor substrate, wherein the termination structure has an active region facing side and a device perimeter facing side;

forming first and second source regions of a first conductivity type in the semiconductor substrate adjacent both the first sides and the second sides of the gate structures; and

forming a third source region in the semiconductor substrate adjacent the active region facing side of the termination structure.

10. The method of claim 9, further comprising:

forming a gate feed structure above the top surface in the edge region in contact with the termination structure and extending over the device perimeter facing side of the termination structure toward a perimeter of the device.

11. The method of claim 9, wherein forming the termination structure comprises:

forming the second trench in the edge region to substantially surround the active region; and

forming the termination structure in the second trench.

12. The method of claim 11, wherein the device has a first side, a second side, a third side, and a fourth side, and wherein forming the second trench comprises:

forming the second trench to include four trench segments in the edge region, wherein a first trench segment is proximate to and parallel with the first side of the device and is parallel with the gate structures, a second trench segment is proximate to and parallel with the second side of the device and is perpendicular to the first trench segment and the gate structures, a third trench segment is proximate to and parallel with the third side of the device and is parallel with the first trench segment and the gate structures and perpendicular to the second trench segment, and a fourth trench segment is proximate to and parallel with the fourth side of the device and is parallel with the second trench segment and perpendicular to the first and third trench segments and the gate structures.

13. The method of claim 12, further comprising:

forming an extension electrode in a third trench in the edge region, wherein the extension electrode extends from the device perimeter facing side of the second trench segment; and

forming a gate feed structure above the top surface in the edge region in contact with an end of the extension electrode and extending toward a perimeter of the device.

14. The method of claim 13, wherein the second trench segment has a zig-zag configuration that includes of a series of straight, parallel trench walls that intersect at angles.

15. The method of claim 13, wherein the second trench segment has a zig-zag configuration that includes of a series of curved parallel trench walls that intersect smoothly at turning points.

16. The method of claim 13, wherein the extension electrode extends at substantially a right angle from the device perimeter facing side of the second trench segment.

17. The method of claim 13, further comprising:

forming a plurality of additional extension electrodes in additional trenches in the edge region, wherein the additional extension electrodes extend from the device perimeter facing side of the second trench segment, and

wherein the gate feed structure contacts ends of the additional extension electrodes.

18. A semiconductor device, comprising:

a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region;

a gate structure formed in a first trench in the active region of the semiconductor substrate, wherein the gate structure has a first side and a second side;

a termination structure formed in a second trench in the edge region of the semiconductor substrate, wherein the termination structure has an active region facing side and a device perimeter facing side;

first and second source regions of a first conductivity type in the semiconductor substrate adjacent both the first side and the second side of the gate structure; and

a third source region in the semiconductor substrate adjacent the active region facing side of the termination structure.

19. The semiconductor device of claim 18, wherein the semiconductor substrate comprises:

a first semiconductor layer having a first conductivity type and defining the bottom surface, wherein the first semiconductor layer corresponds to a drain of the device; and

a second semiconductor layer having the first conductivity type over the first semiconductor layer and defining the top surface, wherein the first and second trenches extend from the top surface into but not through the second semiconductor layer, and portions of the second semiconductor layer underlying the gate structure and the termination structure correspond to drift spaces of the device.

20. The semiconductor device of claim 18, further comprising:

a gate feed structure above the top surface in the edge region in contact with the termination structure and extending over the device perimeter facing side of the termination structure toward a perimeter of the device.

21. The semiconductor device of claim 18, wherein the termination structure substantially surrounds the active region.

22. The semiconductor device of claim 18, further comprising:

an extension electrode in a third trench in the edge region, wherein the extension electrode extends from the device perimeter facing side of the termination structure; and

a gate feed structure above the top surface in the edge region in contact with an end of the extension electrode and extending toward a perimeter of the device.

23. The semiconductor device of claim 22, wherein the extension electrode extends from a trench segment having a zig-zag configuration that includes of a series of straight, parallel trench walls that intersect at angles.

24. The semiconductor device of claim 22, wherein the extension electrode extends from a trench segment having a zig-zag configuration that includes of a series of curved parallel trench walls that intersect smoothly at turning points.

25. The semiconductor device of claim 22, wherein the extension electrode extends at substantially a right angle from the device perimeter facing side of the second trench segment.