Wireless Device with Multi-Port Distributed Antenna

• US 20130308502A1
• Filed: 07/25/2013
• Published: 11/21/2013
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza, Rofougaran, Maryam
• Granted Patent: US 8,831,536 B2
• Time in Patent Office: Days
• US Class Current: 370/278
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01Q 3/30 varying the relative phase between the radiating elements of an array H01Q3/2605, H01Q3/2658, H01Q3/2682, H01Q3/44 take precedence
• CPC Class Codes: H01Q 3/34 by electrical means active lenses or reflecting arrays H01Q3/46
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

Methods and systems for an on-chip and/or on-package T/R switch and antenna are disclosed and may include selectively coupling one or more low noise amplifiers (LNAs) and/or one or more power amplifiers (PAs) to one or more ports of a multi-port distributed antenna utilizing configurable transmit/receive (T/R) switches integrated on a chip with the LNAs and PAs. The LNAs and PAs may be impedance matched to the antenna by coupling them to a port based on a characteristic impedance at the port. The T/R switches may be integrated on a package to which the chip may be coupled. The signals transmitted and received by the antenna may be time division duplexed. The antenna, which may include a microstrip antenna, may be integrated on the chip or the package. The LNA and the PA may be coupled to different ports on the antenna via the T/R switches.

Claims

1-34. -34. (canceled)

35. A wireless device comprising:

a logic block, a multi-port distributed antenna and a processor;

said logic block and/or said processor selectively coupling one or more of a plurality of low noise amplifiers (LNAs) to one or more of a plurality of ports of said multi-port distributed antenna.

36. The wireless device of claim 35, wherein said one or more of said plurality of LNAs are coupled to said one or more of said plurality of ports based on a characteristic impedance of said multi-port distributed antenna at said one or more of said plurality of ports.

37. The wireless device of claim 35, wherein said logic block and/or said process control one or more transmit/receive (T/R) switches in said wireless device.

38. The wireless device of claim 37, wherein said T/R switches comprise CMOS switches.

39. The wireless device of claim 35, wherein time division duplexing signals are transmitted and received by said multi-port distributed antenna.

40. The wireless device of claim 35, wherein said multi-port distributed antenna comprises a microstrip antenna.

41. The wireless device of claim 37, wherein said one or more of said plurality of LNAs are coupled to different ports on said multi-port distributed antenna by said T/R switches.

42. The wireless device of claim 35, wherein said wireless device is configured to utilize a wireless standard selected from the group of standards consisting of GSM, CDMA, CDMA2000, WCDMA, GMS, GPRS, EDGE, WIMAX, WLAN, 3GPP, UMTS, BLUETOOTH, and ZIGBEE standards.

43. The wireless device of claim 37, wherein said processor, said logic block, and said T/R switches are in a single package in said wireless device, and said multi-port distributed antenna is integrated on said single package.

44. The wireless device of claim 35, wherein said processor is in a chip in said wireless device, and said multi-port distributed antenna is integrated in said chip.

45. A wireless device comprising:

a logic block, a multi-port distributed antenna and a processor;

said logic block and/or said processor selectively coupling one or more of a plurality of power amplifiers (PAs) to one or more of a plurality of ports of said multi-port distributed antenna.

46. The wireless device of claim 45, wherein said one or more of said plurality of PAs are coupled to said one or more of said plurality of ports based on a characteristic impedance of said multi-port distributed antenna at said one or more of said plurality of ports.

47. The wireless device of claim 45, wherein said logic block and/or said process control one or more transmit/receive (T/R) switches in said wireless device.

48. The wireless device of claim 47, wherein said T/R switches comprise CMOS switches.

49. The wireless device of claim 45, wherein time division duplexing signals are transmitted and received by said multi-port distributed antenna.

50. The wireless device of claim 45, wherein said multi-port distributed antenna comprises a microstrip antenna.

51. The wireless device of claim 47, wherein said one or more of said plurality of LNAs are coupled to different ports on said multi-port distributed antenna by said T/R switches.

52. The wireless device of claim 45, wherein said wireless device is configured to utilize a wireless standard selected from the group of standards consisting of GSM, CDMA, CDMA2000, WCDMA, GMS, GPRS, EDGE, WIMAX, WLAN, 3GPP, UMTS, BLUETOOTH, and ZIGBEE standards.

53. The wireless device of claim 47, wherein said processor, said logic block, and said T/R switches are in a single package in said wireless device, and said multi-port distributed antenna is integrated on said single package.

54. The wireless device of claim 45, wherein said processor is in a chip in said wireless device, and said multi-port distributed antenna is integrated in said chip.