Combined Accumulator and Maximum/Minimum Comparator

• US 20130321289A1
• Filed: 06/01/2012
• Published: 12/05/2013
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Neodrón Limited (Atlantic IP Services Limited)
• Original Assignee: John Stanley Dubery
• Inventors: DUBERY, John Stanley, HESLOP, Paul, YASSIN, Yahya
• Granted Patent: US 9,046,942 B2
• Time in Patent Office: Days
• US Class Current: 345/173
• CPC Class Codes: G06F 2203/04101 2.5D-digitiser, i.e. digitiser detecting the X/Y position of the input means, finger or stylus, also when it does not touch, but is proximate to the digitiser's interaction surface and also measures the distance of the input means within a short range in the Z direction, possibly with a separate measurement setup
• CPC Class Codes: G06F 3/041 Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

In one embodiment, a method comprises detecting, by a hardware accelerator, that a value has been written to a first location of a memory, the first location identified by a first address. The method further includes adding the value to an accumulated value stored in an accumulator register of the hardware accelerator and storing the result in the accumulator register. The method further includes comparing the value to a maximum value stored in a first register of the hardware accelerator and overwriting the maximum value with the value if the value is greater than the maximum value. The method also includes comparing the value to a minimum value stored in a second register of the hardware accelerator and overwriting the minimum value with the value if the value is less than the minimum value.

Claims

1. A device comprising:

a touch sensor comprising a plurality of nodes;

a microcontroller configured to provide a plurality of drive signals to the touch sensor and detect a touch at one or more of the plurality of nodes, the microcontroller comprising;

a memory including a first location identified by a first address and a second location identified by a second address;

a processor coupled to the memory, the processor operable to write a value to the first location or the second location of the memory by performing an instruction that specifies the value and the first address or the second address; and

a hardware accelerator, the hardware accelerator coupled to the memory and configured to;

perform the following in response to a detection that the value has been written to the first location of the memory;

add the value to an accumulated value stored in an accumulator register of the hardware accelerator and store the result in the accumulator register;

increment a counter of the hardware accelerator;

compare the value to a maximum value stored in a first register of the hardware accelerator and overwrite the maximum value with the value if the value is greater than the maximum value; and

compare the value to a minimum value stored in a second register of the hardware accelerator and overwrite the minimum value with the value if the value is less than the minimum value; and

perform the following in response to a detection that the value has been written to the second location of the memory;

compare the value to the maximum value stored in the first register of the hardware accelerator and overwrite the maximum value with the value if the value is greater than the maximum value; and

compare the value to the minimum value stored in the second register of the hardware accelerator and overwrite the minimum value with the value if the value is less than the minimum value.

2. An apparatus comprising:

a memory including a first location identified by a first address;

a processor coupled to the memory, the processor operable to write a value to a first location of the memory by performing an instruction that specifies the value and the first address; and

a hardware accelerator, the hardware accelerator coupled to the memory and configured to perform the following in response to a determination that the value has been written to the first location;

add the value to an accumulated value stored in an accumulator register of the hardware accelerator and store the result in the accumulator register;

compare the value to a maximum value stored in a first register of the hardware accelerator and overwrite the maximum value with the value if the value is greater than the maximum value; and

compare the value to a minimum value stored in a second register of the hardware accelerator and overwrite the minimum value with the value if the value is less than the minimum value.

3. The apparatus of claim 2, wherein the hardware accelerator is further configured to increment a counter of the hardware accelerator in response to the determination that the value has been written to the first location.

4. The apparatus of claim 2, wherein the hardware accelerator is further configured to add the value to the accumulated value, compare the value to the maximum value, and compare the value to the minimum value within a single clock cycle of the processor.

5. The apparatus of claim 2, wherein the hardware accelerator is further configured to perform the operations of adding the value to the accumulated value, comparing the value to the maximum value, and comparing the value to the minimum value in parallel.

6. The apparatus of claim 2, wherein the value is a first value and the hardware accelerator is further configured to perform the following in response to a determination that a second value has been written to a second location of the memory that is identified by a second address:

compare the second value to the maximum value stored in the first register of the hardware accelerator and overwrite the maximum value with the second value if the second value is greater than the maximum value; and

compare the second value to the minimum value stored in the second register of the hardware accelerator and overwrite the minimum value with the second value if the second value is less than the minimum value.

7. The apparatus of claim 6, wherein the hardware accelerator is further configured to not add the second value to the accumulated value stored in the accumulator register of the hardware accelerator in response to the determination that the second value has been written to the second location.

8. The apparatus of claim 6, wherein the hardware accelerator further comprises at least one multiplexor for coupling the first location of the memory or the second location of the memory to logic that performs the comparisons with the minimum and maximum values.

9. The apparatus of claim 2, wherein the hardware accelerator is further configured to barrel shift the accumulated value to generate a shifted accumulated value and provide the shifted accumulated value to the memory.

10. The apparatus of claim 2, wherein the hardware accelerator is further configured to detect that a multiplier has performed an operation and to add an output of the multiplier to the accumulated value in response to the detection that the multiplier has performed the operation.

11. The apparatus of claim 10, wherein the hardware accelerator is further configured to increment a counter of the hardware accelerator in response to the detection that the multiplier has performed the operation.

12. The apparatus of claim 10, wherein the hardware accelerator further comprises logic for negating the output of the multiplier and adding the negated output to the accumulated value.

13. A method comprising:

detecting, by a hardware accelerator, that a value has been written to a first location of a memory, the first location identified by a first address;

performing, by the hardware accelerator, the following in response to detecting that the value has been written to the first location of the memory;

adding the value to an accumulated value stored in an accumulator register of the hardware accelerator and storing the result in the accumulator register;

comparing the value to a maximum value stored in a first register of the hardware accelerator and overwriting the maximum value with the value if the value is greater than the maximum value; and

comparing the value to a minimum value stored in a second register of the hardware accelerator and overwriting the minimum value with the value if the value is less than the minimum value.

14. The method of claim 13, further comprising incrementing a counter of the hardware accelerator in response to the determination that the value has been written to the first location.

15. The method of claim 13, wherein the value is added to the accumulated value, the value is compared to the maximum value, and the value is compared to the minimum value within a single clock cycle of a processor that wrote the value to the first location of the memory.

16. The method of claim 13, wherein the operations of adding the value to the accumulated value, comparing the value to the maximum value, and comparing the value to the minimum value are performed in parallel.

17. The method of claim 13, wherein the value is a first value and the method further comprises performing the following in response to a determination that a second value has been written to a second location of the memory that is identified by a second address:

comparing the second value to the maximum value stored in the first register of the hardware accelerator and overwriting the maximum value with the second value if the second value is greater than the maximum value; and

comparing the second value to the minimum value stored in the second register of the hardware accelerator and overwriting the minimum value with the second value if the second value is less than the minimum value.

18. The method of claim 17, further comprising selecting one of the first location of the memory or the second location of the memory to couple to logic that performs the comparisons with the minimum and maximum values.

19. The method of claim 13, further comprising shifting the accumulated value by a predetermined number of bits to generate a shifted accumulated value and providing the shifted accumulated value to the memory.

20. The method of claim 13, further comprising:

detecting that a multiplier has performed an operation; and

adding an output of the multiplier to the accumulated value in response to the detection that the multiplier has performed the operation.