DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME

• US 20130323883A1
• Filed: 08/06/2013
• Published: 12/05/2013
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YU, Chen-Hua, CHIOU, Wen-Chih, LIAO, Ebin, WU, Tsang-Jiuh
• Granted Patent: US 9,087,878 B2
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Abstract

A method includes forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth. The method further includes forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening and forming a conductive layer on the insulation structure to fill the opening. A first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

Claims

1. A method, comprising:

forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth;

forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening; and

forming a conductive layer on the insulation structure to fill the opening;

wherein a first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

2. The method of claim 1, wherein forming the insulation structure comprises:

performing a first deposition process to form a first insulation layer adjacent to the silicon substrate, and

performing a second deposition process to form a second insulation layer adjacent to the conductive layer;

wherein the second deposition process is different from the first deposition process.

3. The method of claim 2, wherein the first deposition process is a thermal oxidation process.

4. The method of claim 3, wherein the second deposition process includes at least one of a sub-atmospheric chemical vapor deposition (SACVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and a plasma-enhanced atomic layer deposition (PEALD) process.

5. The method of claim 4, wherein the second insulation layer has an isotropic etching rate greater than an isotropic etching rate of the first insulation layer.

6. The method of claim 2, wherein the first deposition process includes at least one of a sub-atmospheric chemical vapor deposition (SACVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and a plasma-enhanced atomic layer deposition (PEALD) process.

7. The method of claim 6, wherein the second deposition process is a thermal oxidation process.

8. The method of claim 2, wherein the first deposition process forms a first oxide layer adjacent to the silicon substrate and the second deposition process forms a second oxide layer adjacent to the conductive layer.

9. The method of claim 1, wherein the step of forming a conductive layer on the insulating structure forms a copper layer.

10. The method of claim 9, wherein the conductive layer comprises a diffusion barrier layer underlying the copper layer.

11. The method of claim 10, further comprising forming an integrated circuit die electrically coupled to the conductive layer formed in the silicon substrate.

12. A method, comprising:

forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth;

forming a first insulation layer on the silicon substrate along the sidewalls and the bottom of the opening;

performing a thermal oxidation process to form a second insulation layer along the sidewalls and the bottom of the opening; and

forming a conductive layer over the second insulation layer to fill the opening;

wherein an interface between the first insulation layer or the second insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm.

13. The method of claim 12, wherein performing the thermal oxidation process comprises forming the second insulation layer between the sidewalls and the bottom of the opening and the first insulation layer.

14. The method of claim 12, wherein forming the opening comprises:

forming a hardmask layer over the silicon substrate;

forming a photoresist layer over the hardmask layer;

patterning the photoresist layer to form a photoresist opening;

etching the hardmask through the photoresist opening to form a hardmask opening; and

etching the silicon substrate to form the opening.

15. The method of claim 14, wherein etching the silicon substrate comprises performing at least one of a plasma etching process, a chemical etching process, a reactive ion etching process, or laser drill process.

16. The method of claim 12, further comprising performing a chemical mechanical polishing (CMP) process to make a top surface of the conductive layer coplanar with the top surface of the silicon substrate.

17. A method, comprising:

forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth;

forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening, wherein an interface between the insulation structure layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm;

forming a conductive layer over the second insulation layer to fill the opening;

thinning a bottom surface of the silicon substrate opposite the top surface of the silicon substrate; and

bonding at least one die to the thinned silicon substrate.

18. The method of claim 17, wherein forming the insulation structure comprises performing a sub-atmospheric chemical vapor deposition (SACVD) process at a pressure ranging from about 100 torr to about 600 torr.

19. The method of claim 18, wherein performing the SACVD process comprises using a mixture of ozone and TEOS (Tetra-Ethyl-Ortho-Silicate) free of plasma.

20. The method of claim 17, further comprising:

forming a barrier layer on the insulation structure, the barrier layer comprises at least one of titanium, tantalum or tungsten; and

plating a seed layer on the barrier layer, wherein the conductive layer is formed on the seed layer.