Semiconductor Device

• US 20130328050A1
• Filed: 08/15/2013
• Published: 12/12/2013
• Est. Priority Date: 09/15/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakakura, Masayuki, Yamazaki, Shunpei, Higaki, Yoshinari
• Granted Patent: US 8,786,794 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

Claims

1. (canceled)

2. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

a semiconductor layer over the gate insulating layer; and

a source electrode and a drain electrode, over the semiconductor layer,

wherein one of the source electrode and the drain electrode is electrically connected to the semiconductor layer, and has a first electrode layer and a second electrode layer,

wherein the second electrode layer is formed on the first electrode layer,

wherein the first electrode layer comprises titanium,

wherein the second electrode layer comprises aluminum,

wherein a first width of the first electrode layer is larger than a second width of the second electrode layer,

wherein an upper surface of the second electrode layer is in contact with an insulating layer,

wherein the first electrode layer is in contact with a pixel electrode,

wherein the semiconductor layer comprises an amorphous silicon, and

wherein the pixel electrode comprises an ITO.

3. The semiconductor device according to claim 2,

wherein the second electrode layer is in contact with the pixel electrode.

4. The semiconductor device according to claim 2, further comprising:

a second insulating layer between the semiconductor layer and the one of the source electrode and the drain electrode.

5. The semiconductor device according to claim 2,

wherein the gate electrode comprises tantalum nitride and tungsten.

6. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

a semiconductor layer over the gate insulating layer;

a source electrode and a drain electrode, over the semiconductor layer;

a pixel electrode electrically connected to one of the source electrode and the drain electrode;

an orientation film over the pixel electrode; and

a liquid crystal layer over the orientation film,

wherein one of the source electrode and the drain electrode is electrically connected to the semiconductor layer, and has a first electrode layer and a second electrode layer,

wherein the second electrode layer is formed on the first electrode layer,

wherein the first electrode layer comprises titanium,

wherein the second electrode layer comprises aluminum,

wherein a first width of the first electrode layer is larger than a second width of the second electrode layer,

wherein an upper surface of the second electrode layer is in contact with an insulating layer,

wherein the first electrode layer is in contact with the pixel electrode,

wherein the semiconductor layer comprises an amorphous silicon, and

wherein the pixel electrode comprises an ITO.

7. The semiconductor device according to claim 6,

wherein the second electrode layer is in contact with the pixel electrode.

8. The semiconductor device according to claim 6, further comprising:

a second insulating layer between the semiconductor layer and the one of the source electrode and the drain electrode.

9. The semiconductor device according to claim 6,

wherein the gate electrode comprises tantalum nitride and tungsten.

10. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

a semiconductor layer over the gate insulating layer;

a source electrode and a drain electrode, over the semiconductor layer;

a pixel electrode electrically connected to one of the source electrode and the drain electrode;

an orientation film over the pixel electrode; and

a liquid crystal layer over the orientation film,

wherein one of the source electrode and the drain electrode is electrically connected to the semiconductor layer, and has a first electrode layer and a second electrode layer,

wherein the second electrode layer is formed on the first electrode layer,

wherein the first electrode layer comprises titanium,

wherein the second electrode layer comprises aluminum,

wherein a first width of the first electrode layer is larger than a second width of the second electrode layer,

wherein an upper surface of the second electrode layer is in contact with an insulating layer,

wherein the first electrode layer is in contact with the pixel electrode,

wherein the semiconductor layer comprises an amorphous silicon,

wherein the pixel electrode comprises an ITO, and

wherein the gate electrode, the semiconductor layer, the source electrode and the drain electrode are provided in a pixel region.

11. The semiconductor device according to claim 10,

wherein the second electrode layer is in contact with the pixel electrode.

12. The semiconductor device according to claim 10, further comprising:

a second insulating layer between the semiconductor layer and the one of the source electrode and the drain electrode.

13. The semiconductor device according to claim 10,

wherein the gate electrode comprises tantalum nitride and tungsten.